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/Documentation/devicetree/bindings/dma/
Dsifive,fu540-c000-pdma.yaml4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
32 - microchip,mpfs-pdma
33 - sifive,fu540-c000-pdma
36 Should be "sifive,<chip>-pdma" and "sifive,pdma<version>".
38 "sifive,fu540-c000-pdma" for the SiFive PDMA v0 as integrated onto the
39 SiFive FU540 chip resp and "sifive,pdma0" for the SiFive PDMA v0 IP block
68 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
Dmarvell,mmp-dma.yaml18 - marvell,pdma-1.0
54 - marvell,pdma-1.0
67 compatible = "marvell,pdma-1.0";
/Documentation/devicetree/bindings/crypto/
Dartpec6-crypto.txt1 Axis crypto engine with PDMA interface.
7 - reg: Base address and size for the PDMA register area.
8 - interrupts: Interrupt handle for the PDMA interrupt line.
/Documentation/devicetree/bindings/net/
Dairoha,en7581-eth.yaml44 - description: PDMA irq
52 - const: pdma
120 reset-names = "fe", "pdma", "qdma", "xsi-mac",
/Documentation/devicetree/bindings/mmc/
Dsynopsys-dw-mshc.yaml88 dmas = <&pdma 12>;
/Documentation/devicetree/bindings/mtd/
Dmarvell,nand-controller.yaml215 dmas = <&pdma 97 3>;
/Documentation/devicetree/bindings/edac/
Dsocfpga-eccmgr.txt204 altr,ecc-parent = <&pdma>;
366 altr,ecc-parent = <&pdma>;
/Documentation/devicetree/bindings/pinctrl/
Dmarvell,dove-pinctrl.txt8 - clocks: (optional) phandle of pdma clock
/Documentation/devicetree/bindings/dma/ti/
Dk3-udma.yaml38 legacy, non PSI-L native peripherals. In the later case a special, small PDMA
Dk3-pktdma.yaml20 with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
Dk3-bcdma.yaml25 with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
/Documentation/devicetree/bindings/clock/
Dmvebu-gated-clock.txt149 22 pdma Peripheral DMA
Dsamsung,exynos5433-clock.yaml39 # CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs