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/Documentation/devicetree/bindings/cpufreq/
Dapple,cluster-cpufreq.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple SoC cluster cpufreq device
10 - Hector Martin <marcan@marcan.st>
13 Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
14 the cluster management register block. This binding uses the standard
15 operating-points-v2 table to define the CPU performance states, with the
16 opp-level property specifying the hardware p-state index for that level.
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Dcpufreq-qcom-hw.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21 - description: v1 of CPUFREQ HW
23 - enum:
24 - qcom,qcm2290-cpufreq-hw
25 - qcom,sc7180-cpufreq-hw
26 - qcom,sdm670-cpufreq-hw
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/Documentation/admin-guide/pm/
Dintel_uncore_frequency_scaling.rst1 .. SPDX-License-Identifier: GPL-2.0
8 :Copyright: |copy| 2022-2023 Intel Corporation
13 ------------
22 the scaling min/max frequencies via cpufreq sysfs to improve CPU performance.
30 ---------------
33 `/sys/devices/system/cpu/intel_uncore_frequency/`.
36 uncore scaling control is per die in multiple die/package SoCs or per
37 package for single die per package SoCs. The name represents the
45 This is a read-only attribute. If users adjust max_freq_khz,
50 This is a read-only attribute. If users adjust min_freq_khz,
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/Documentation/devicetree/bindings/cpu/
Dcpu-topology.txt2 CPU topology binding description
6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
25 CPU topology bindings allow one to associate cpu nodes with hierarchical groups
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/Documentation/devicetree/bindings/arm/marvell/
Dap80x-system-controller.txt6 registers giving access to numerous features: clocks, pin-muxing and
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
18 -------
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
31 - compatible: must be one of:
32 * "marvell,ap806-clock"
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/Documentation/ABI/stable/
Dsysfs-devices-system-cpu1 What: /sys/devices/system/cpu/dscr_default
2 Date: 13-May-2014
6 /sys/devices/system/cpu/cpuN/dscr on all CPUs.
9 all per-CPU defaults at the same time.
12 What: /sys/devices/system/cpu/cpu[0-9]+/dscr
13 Date: 13-May-2014
17 a CPU.
22 on any CPU where it executes (overriding the value described
27 What: /sys/devices/system/cpu/cpuX/topology/physical_package_id
33 What: /sys/devices/system/cpu/cpuX/topology/die_id
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/Documentation/admin-guide/perf/
Dqcom_l2_pmu.rst2 Qualcomm Technologies Level-2 Cache Performance Monitoring Unit (PMU)
7 own PMU. Each cluster has one or more CPUs associated with it.
17 Events can be envisioned as a 2-dimensional array. Each column represents
23 the code (array row) and G specifies the group (column) 0-7.
29 consisting of one CPU per cluster which will be used to handle all the PMU
30 events on that cluster.
34 perf stat -e l2cache_0/config=0x001/,l2cache_0/config=0x042/ -a sleep 1
36 perf stat -e l2cache_0/config=0xfe/ -C 2 sleep 1
39 not work. Per-task perf sessions are not supported.
/Documentation/devicetree/bindings/interrupt-controller/
Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
22 - Automatic masking on event delivery (auto-ack)
23 - Software triggering (ORed with hw line)
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/Documentation/devicetree/bindings/arm/
Darm,cci-400.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
19 space and multiple sets of interface control registers, one per slave
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
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Dpsci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
15 processors") can be used by Linux to initiate various CPU-centric power
18 Issue A of the specification describes functions for CPU suspend, hotplug
25 r0 => 32-bit Function ID / return value
26 {r1 - r3} => Parameters
40 - description:
44 - description:
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/Documentation/devicetree/bindings/remoteproc/
Dti,k3-r5f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14 processor subsystems/clusters (R5FSS). The dual core cluster can be used
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
27 Each Dual-Core R5F sub-system is represented as a single DTS node
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Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
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/Documentation/devicetree/bindings/opp/
Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
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/Documentation/filesystems/
Dgfs2-glocks.rst1 .. SPDX-License-Identifier: GPL-2.0
13 2. A non-blocking bit lock, GLF_LOCK, which is used to prevent other
56 Table of glock operations and per type constants:
77 prevent a situation where locks are being bounced around the cluster
118 5. Transaction glock (via gfs2_trans_begin) for non-read operations
122 There are two glocks per inode. One deals with access to the inode
126 is on a per-inode basis. Locking of rgrps is on a per rgrp basis.
127 In general we prefer to lock local locks prior to cluster locks.
130 ----------------
134 super block stats are done on a per cpu basis in order to
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Df2fs.rst1 .. SPDX-License-Identifier: GPL-2.0
4 WHAT IS Flash-Friendly File System (F2FS)?
7 NAND flash memory-based storage devices, such as SSD, eMMC, and SD cards, have
13 F2FS is a file system exploiting NAND flash memory-based storage devices, which
14 is based on Log-structured File System (LFS). The design has been focused on
18 Since a NAND flash memory-based storage device shows different characteristic
20 F2FS and its tools support various parameters not only for configuring on-disk
26 - git://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fs-tools.git
30 - linux-f2fs-devel@lists.sourceforge.net
34 - https://bugzilla.kernel.org/enter_bug.cgi?product=File%20System&component=f2fs
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/Documentation/trace/coresight/
Dultrasoc-smb.rst1 .. SPDX-License-Identifier: GPL-2.0
4 UltraSoc - HW Assisted Tracing on SoC
10 ------------
12 UltraSoc SMB is a per SCCL (Super CPU Cluster) hardware. It provides a
13 way to buffer and store CPU trace messages in a region of shared system
18 ---------------------------
42 -----------------
49 is the configuration base address of the device, the second one is the 32-bit
63 ToUUID("ab02a46b-74c7-45a2-bd68-f7d344ef2153"), \
70 ToUUID("3ecbc8b6-1d0e-4fb3-8107-e627f805c6cd"), \
/Documentation/admin-guide/sysctl/
Dnet.rst9 - Terrehon Bowden <terrehon@pacbell.net>
10 - Bodo Bauer <bb@ricochet.net>
14 - Jorge Nerin <comandante@zaralinux.com>
18 - Shen Feng <shen@cn.fujitsu.com>
22 ------------------------------------------------------------------------------
47 1. /proc/sys/net/core - Network core options
51 --------------
60 translate these BPF proglets into native CPU instructions. There are
63 - x86_64
64 - x86_32
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Dvm.rst13 ------------------------------------------------------------------------------
27 - admin_reserve_kbytes
28 - compact_memory
29 - compaction_proactiveness
30 - compact_unevictable_allowed
31 - dirty_background_bytes
32 - dirty_background_ratio
33 - dirty_bytes
34 - dirty_expire_centisecs
35 - dirty_ratio
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/Documentation/networking/device_drivers/ethernet/intel/
De1000.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999 - 2013 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Speed and Duplex Configuration
16 - Additional Configurations
17 - Support
50 -------
54 :Valid Range: 0x01-0x0F, 0x20-0x2F
57 This parameter is a bit-mask that specifies the speed and duplex settings
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/Documentation/trace/
Dhisi-ptt.rst1 .. SPDX-License-Identifier: GPL-2.0
23 +--------------Core 0-------+
25 | | [Root Port]---[Endpoint]
26 | | [Root Port]---[Endpoint]
27 | | [Root Port]---[Endpoint]
28 Root Complex |------Core 1-------+
30 | | [Root Port]---[ Switch ]---[Endpoint]
31 | | [Root Port]---[Endpoint] `-[Endpoint]
32 | | [Root Port]---[Endpoint]
33 +---------------------------+
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/Documentation/sound/designs/
Dcompress-offload.rst2 ALSA Compress-Offload API
5 Pierre-Louis.Bossart <pierre-louis.bossart@linux.intel.com>
18 in system-on-chip designs, and DSPs are also integrated in audio
20 reduction of power consumption compared to host-based
27 provide a control and data-streaming interface for audio DSPs.
29 The design of this API was inspired by the 2-year experience with the
39 - separation between byte counts and time. Compressed formats may have
40 a header per file, per frame, or no header at all. The payload size
41 may vary from frame-to-frame. As a result, it is not possible to
44 reliable audio-video synchronization, which requires precise
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/Documentation/admin-guide/
Dkernel-parameters.txt16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nospcr -- disable console in ACPI SPCR table as
41 If set to vendor, prefer vendor-specific driver
73 Documentation/firmware-guide/acpi/debug.rst for more information about
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/Documentation/arch/x86/
Dresctrl.rst1 .. SPDX-License-Identifier: GPL-2.0
9 :Authors: - Fenghua Yu <fenghua.yu@intel.com>
10 - Tony Luck <tony.luck@intel.com>
11 - Vikas Shivappa <vikas.shivappa@intel.com>
38 # mount -t resctrl resctrl [-o cdp[,cdpl2][,mba_MBps][,debug]] /sys/fs/resctrl
57 pseudo-locking is a unique way of using cache control to "pin" or
59 "Cache Pseudo-Locking".
96 own settings for cache use which can over-ride
128 Corresponding region is pseudo-locked. No
131 Indicates if non-contiguous 1s value in CBM is supported.
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/Documentation/core-api/
Dassoc_array.rst48 The implementation uses a tree of 16-pointer nodes internally that are indexed
51 what would otherwise be a series of single-occupancy nodes. Further, nodes
68 ./script/config -e ASSOCIATIVE_ARRAY
72 -----------
82 after an RCU grace period has passed - thus allowing access functions to
112 ----------------
126 This should return a chunk of caller-supplied index key starting at the
137 rather than from a caller-supplied index key.
153 differs from the given index key or -1 if they are the same.
166 ----------------------
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/Documentation/virt/kvm/
Dapi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
13 - System ioctls: These query and set global attributes which affect the
17 - VM ioctls: These query and set attributes that affect an entire virtual
24 - vcpu ioctls: These query and set attributes that control the operation
25 of a single virtual cpu.
32 - device ioctls: These query and set attributes that control the operation
46 create a virtual cpu or device and return a file descriptor pointing to
80 facility that allows backward-compatible extensions to the API to be
104 the ioctl returns -ENOTTY.
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