Searched +full:per +full:- +full:port (Results 1 – 25 of 236) sorted by relevance
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | tda1997x.txt | 1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
5 The TDA19971 Video port output pins can be used as follows:
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
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| /Documentation/devicetree/bindings/display/imx/ |
| D | fsl,imx-lcdc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sascha Hauer <s.hauer@pengutronix.de>
11 - Pengutronix Kernel Team <kernel@pengutronix.de>
16 - enum:
17 - fsl,imx1-fb
18 - fsl,imx21-fb
19 - items:
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,embedded-trace-extension.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Suzuki K Poulose <suzuki.poulose@arm.com>
12 - Mathieu Poirier <mathieu.poirier@linaro.org>
15 Arm Embedded Trace Extension(ETE) is a per CPU trace component that
19 components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
21 legacy CoreSight components, a node must be listed per instance, along
22 with any optional connection graph as per the coresight bindings.
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| D | arm,coresight-tmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
32 const: arm,coresight-tmc
34 - compatible
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | adi,adv7511.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
21 - adi,adv7511
22 - adi,adv7511w
23 - adi,adv7513
37 reg-names:
40 needing a non-default address.
43 - const: main
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| D | ps8640.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Boichat <drinkcat@chromium.org>
13 The PS8640 is a low power MIPI-to-eDP video format converter supporting
16 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
18 3.24Gbit/sec per lane.
28 powerdown-gpios:
32 reset-gpios:
36 vdd12-supply:
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| D | nxp,tda998x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Russell King <linux@armlinux.org.uk>
22 video-ports:
30 audio-ports:
32 Array of 2 values per DAI (Documentation/sound/soc/dai.rst).
35 $ref: /schemas/types.yaml#/definitions/uint32-matrix
40 - description: |
42 (see include/dt-bindings/display/tda998x.h).
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| /Documentation/networking/device_drivers/ethernet/freescale/dpaa2/ |
| D | switch-driver.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 The driver uses the switch device driver model and exposes each switch port as
24 [dpaa2-eth] [dpaa2-eth] [ dpaa2-switch ]
30 | ---------- | [DPMAC] [DPMAC]
31 ------------------------------- | |
38 The dpaa2-switch driver probes on DPSW devices found on the fsl-mc bus. These
40 file - DataPath Layout (DPL) - or at runtime using the DPAA2 object APIs
43 At the moment, the dpaa2-switch driver imposes the following restrictions on
48 done, ie when not under a bridge, each switch port will have its own FDB.
53 * Both the broadcast and flooding configuration should be per FDB. This
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| /Documentation/devicetree/bindings/media/ |
| D | cdns,csi2tx.txt | 1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
20 - phy-names: must contain "dphy"
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| D | nxp,imx8-isi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8-isi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
16 number and nature is SoC-dependent. They cover both capture interfaces (MIPI
17 CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
22 - fsl,imx8mn-isi
23 - fsl,imx8mp-isi
24 - fsl,imx93-isi
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | renesas,rza1-ports.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
18 Each "port" features up to 16 pins, each of them configurable for GPIO
19 function (port mode) or in alternate function mode.
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| /Documentation/scsi/ |
| D | advansys.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
9 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
10 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
21 - ABP-480 - Bus-Master CardBus (16 CDB)
24 - ABP510/5150 - Bus-Master ISA (240 CDB)
25 - ABP5140 - Bus-Master ISA PnP (16 CDB)
26 - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
27 - ABP902/3902 - Bus-Master PCI (16 CDB)
28 - ABP3905 - Bus-Master PCI (16 CDB)
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| /Documentation/devicetree/bindings/net/ |
| D | marvell,pp2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcin Wojtas <mw@semihalf.com>
11 - Russell King <linux@armlinux.org>
21 - marvell,armada-375-pp2
22 - marvell,armada-7k-pp22
28 "#address-cells":
31 "#size-cells":
37 - description: main controller clock
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| /Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,video.txt | 2 -------------------------------
5 ---------------
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
18 in Documentation/devicetree/bindings/dma/dma.txt) per port. Each port
19 requires a DMA channel with the identifier string set to "port" followed by
20 the port index.
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
24 Required port properties:
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| /Documentation/arch/s390/ |
| D | pci.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 - Pierre Morel
17 -----------------------
25 Ignore the RID field and force use of one PCI domain per PCI function.
28 ---------------
36 - /sys/kernel/debug/s390dbf/pci_msg/sprintf
56 - /sys/bus/pci/slots/XXXXXXXX/power
64 - function_id
67 - function_handle
68 Low-level identifier used for a configured PCI function.
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| /Documentation/networking/device_drivers/ethernet/intel/ |
| D | i40e.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
47 ----------------------
49 …intel.com/content/dam/www/public/us/en/documents/release-notes/xl710-ethernet-controller-feature-m…
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| /Documentation/devicetree/bindings/sound/ |
| D | nvidia,tegra210-mvc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-mvc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 signal path. It can be used in input or output signal path for per-stream
14 multi-channel (up to 7.1 channels) stream. An independent mute control is
18 - Jon Hunter <jonathanh@nvidia.com>
19 - Mohan Kumar <mkumard@nvidia.com>
20 - Sameer Pujar <spujar@nvidia.com>
23 - $ref: dai-common.yaml#
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| /Documentation/networking/ |
| D | rds.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 http://oss.oracle.com/pipermail/rds-devel/2007-November/000228.html
22 cluster - so in a cluster with N processes you need N sockets, in contrast
23 to N*N if you use a connection-oriented socket transport like TCP.
25 RDS is not Infiniband-specific; it was designed to support different
29 The high-level semantics of RDS from the application's point of view are
33 RDS uses IPv4 addresses and 16bit port numbers to identify
39 transport has to be IP-based. In fact, RDS over IB uses a
43 The port space is entirely independent of UDP, TCP or any other
59 a active-active HA scenario), but only as long as the address
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| /Documentation/networking/dsa/ |
| D | dsa.rst | 19 they configured/queried a switch port network device or a regular network
22 An Ethernet switch typically comprises multiple front-panel ports and one
24 presence of a management port connected to an Ethernet controller capable of
27 gateways, or even top-of-rack switches. This host Ethernet controller will
36 For each front-panel port, DSA creates specialized network devices which are
37 used as controlling and data-flowing endpoints for use by the Linux networking
46 - what port is this frame coming from
47 - what was the reason why this frame got forwarded
48 - how to send CPU originated traffic to specific ports
52 on Port-based VLAN IDs).
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| /Documentation/devicetree/bindings/usb/ |
| D | pxa-usb.txt | 6 - compatible: Should be "marvell,pxa-ohci" for USB controllers
10 - "marvell,enable-port1", "marvell,enable-port2", "marvell,enable-port3"
11 If present, enables the appropriate USB port of the controller.
12 - "marvell,port-mode" selects the mode of the ports:
16 - "marvell,power-sense-low" - power sense pin is low-active.
17 - "marvell,power-control-low" - power control pin is low-active.
18 - "marvell,no-oc-protection" - disable over-current protection.
19 - "marvell,oc-mode-perport" - enable per-port over-current protection.
20 - "marvell,power_on_delay" Power On to Power Good time - in ms.
25 compatible = "marvell,pxa-ohci";
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| /Documentation/devicetree/bindings/hsi/ |
| D | client-devices.txt | 1 Each HSI port is supposed to have one child node, which
2 symbols the remote device connected to the HSI port. The
7 - hsi-channel-ids: A list of channel ids
9 - hsi-rx-mode: Receiver Bit transmission mode ("stream" or "frame")
10 - hsi-tx-mode: Transmitter Bit transmission mode ("stream" or "frame")
11 - hsi-mode: May be used instead hsi-rx-mode and hsi-tx-mode if
14 - hsi-speed-kbps: Max bit transmission speed in kbit/s
15 - hsi-flow: RX flow type ("synchronized" or "pipeline")
16 - hsi-arb-mode: Arbitration mode for TX frame ("round-robin", "priority")
20 - hsi-channel-names: A list with one name per channel specified in the
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| /Documentation/devicetree/bindings/ata/ |
| D | faraday,ftide010.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
15 platform. The controller can do PIO modes 0 through 4, Multi-word DMA
22 The timing properties are unique per-SoC, not per-board.
27 - const: faraday,ftide010
28 - items:
29 - const: cortina,gemini-pata
30 - const: faraday,ftide010
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| /Documentation/devicetree/bindings/display/ti/ |
| D | ti,k2g-dss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/ti/ti,k2g-dss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jyri Sarha <jsarha@ti.com>
12 - Tomi Valkeinen <tomi.valkeinen@ti.com>
15 The K2G DSS is an ultra-light version of TI Keystone Display
16 SubSystem. It has only one output port and video plane. The
21 const: ti,k2g-dss
25 - description: cfg DSS top level
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| /Documentation/leds/ |
| D | ledtrig-usbport.rst | 2 USB port LED trigger
6 in a given port. It simply turns on LED when device appears and turns it off
11 echoing "1" to a chosen port.
24 2) Device with a physical port handled by few controllers
27 Some devices may have one controller per PHY standard. E.g. USB 3.0 physical
28 port may be handled by ohci-platform, ehci-platform and xhci-hcd. If there is
38 Documentation/ABI/testing/sysfs-class-led-trigger-usbport
40 Example use-case::
43 echo 1 > ports/usb1-port1
44 echo 1 > ports/usb2-port1
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| /Documentation/devicetree/bindings/display/ |
| D | st,stm32mp25-lvds.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32mp25-lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
15 LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
19 - LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input
21 - LVDS PHY: parallelize the data and drives the LVDS data lanes
22 - LVDS wrapper: handles top-level settings
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