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/Documentation/devicetree/bindings/dvfs/
Dperformance-domain.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dvfs/performance-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic performance domains
10 - Sudeep Holla <sudeep.holla@arm.com>
13 This binding is intended for performance management of groups of devices or
14 CPUs that run in the same performance domain. Performance domains must not
15 be confused with power domains. A performance domain is defined by a set
16 of devices that always have to run at the same performance level. For a given
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/Documentation/devicetree/bindings/cpufreq/
Dapple,cluster-cpufreq.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
13 Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
15 operating-points-v2 table to define the CPU performance states, with the
16 opp-level property specifying the hardware p-state index for that level.
21 - items:
22 - enum:
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Dqemu,virtual-cpufreq.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/qemu,virtual-cpufreq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Dai <davidai@google.com>
11 - Saravana Kannan <saravanak@google.com>
14 Virtual CPUFreq is a virtualized driver in guest kernels that sends performance
16 is associated with a performance domain which can be shared with other vCPUs.
17 Each performance domain has its own set of registers for performance controls.
21 const: qemu,virtual-cpufreq
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Dcpufreq-mediatek-hw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Yuan <hector.yuan@mediatek.com>
19 const: mediatek,cpufreq-hw
29 "#performance-domain-cells":
31 Number of cells in a performance domain specifier.
33 performance domains.
37 - compatible
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/Documentation/arch/powerpc/
Dassociativity.rst6 domains of substantially similar mean performance relative to resources outside
8 performance relative to each other than relative to other resources subsets
9 are represented as being members of a sub-grouping domain. This performance
11 From the platform view, these groups are also referred to as domains.
17 Hypervisor indicates the type/form of associativity used via "ibm,architecture-vec-5 property".
18 Bit 0 of byte 5 in the "ibm,architecture-vec-5" property indicates usage of Form 0 or Form 1.
20 bit 2 of byte 5 in the "ibm,architecture-vec-5" property is used.
23 ------
27 ------
28 With Form 1 a combination of ibm,associativity-reference-points, and ibm,associativity
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/Documentation/devicetree/bindings/power/
Dpower-domain.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/power-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic PM domains
10 - Rafael J. Wysocki <rjw@rjwysocki.net>
11 - Kevin Hilman <khilman@kernel.org>
12 - Ulf Hansson <ulf.hansson@linaro.org>
15 System on chip designs are often divided into multiple PM domains that can be
17 leakage current. Moreover, in some cases the similar PM domains may also be
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Dapple,pmgr-pwrstate.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/apple,pmgr-pwrstate.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
13 - $ref: power-domain.yaml#
18 performance features. This binding describes the device power
23 Documentation/devicetree/bindings/power/power-domain.yaml.
25 represented via power-domains relationships between these nodes.
28 for the top-level PMGR node documentation.
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/Documentation/scheduler/
Dsched-energy.rst6 ---------------
25 please refer to its documentation (see Documentation/power/energy-model.rst).
29 -----------------------------
32 - energy = [joule] (resource like a battery on powered devices)
33 - power = energy/time = [joule/second] = [watt]
38 performance [inst/s]
39 --------------------
45 -----------
48 while still getting 'good' performance. It is essentially an alternative
49 optimization objective to the current performance-only objective for the
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/Documentation/power/
Denergy-model.rst1 .. SPDX-License-Identifier: GPL-2.0
8 -----------
11 the power consumed by devices at various performance levels, and the kernel
12 subsystems willing to use that information to make energy-aware decisions.
18 each and every client subsystem to re-implement support for each and every
23 The power values might be expressed in micro-Watts or in an 'abstract scale'.
26 can be found in the Energy-Aware Scheduler documentation
27 Documentation/scheduler/sched-energy.rst. For some subsystems like thermal or
30 thus the real micro-Watts might be needed. An example of these requirements can
32 Documentation/driver-api/thermal/power_allocator.rst.
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/Documentation/admin-guide/pm/
Dintel_uncore_frequency_scaling.rst1 .. SPDX-License-Identifier: GPL-2.0
8 :Copyright: |copy| 2022-2023 Intel Corporation
13 ------------
17 performance, SoCs have internal algorithms for scaling uncore frequency. These
20 It is possible that users have different expectations of uncore performance and
22 the scaling min/max frequencies via cpufreq sysfs to improve CPU performance.
25 different core and uncore performance at distinct phases and they may want to
27 improve overall performance.
30 ---------------
45 This is a read-only attribute. If users adjust max_freq_khz,
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/Documentation/devicetree/bindings/clock/
Dqcom,sm8350-videocc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8350-videocc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konradybcio@kernel.org>
14 domains on Qualcomm SoCs.
17 include/dt-bindings/clock/qcom,videocc-sm8350.h
18 include/dt-bindings/reset/qcom,videocc-sm8350.h
23 - qcom,sc8280xp-videocc
24 - qcom,sm8350-videocc
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Dqcom,sm8450-videocc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <quic_tdas@quicinc.com>
11 - Jagadeesh Kona <quic_jkona@quicinc.com>
15 domains on SM8450.
18 include/dt-bindings/clock/qcom,sm8450-videocc.h
19 include/dt-bindings/clock/qcom,sm8650-videocc.h
24 - qcom,sm8450-videocc
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Dqcom,sm8150-camcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8150-camcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
14 power domains on SM8150.
16 See also:: include/dt-bindings/clock/qcom,sm8150-camcc.h
20 const: qcom,sm8150-camcc
27 - description: Board XO source
28 - description: Camera AHB clock from GCC
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Dqcom,sm6375-gpucc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konradybcio@kernel.org>
14 domains on Qualcomm SoCs.
16 See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h
21 - qcom,sm6375-gpucc
25 - description: Board XO source
26 - description: GPLL0 main branch source
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Dqcom,qcm2290-gpucc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qcm2290-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konradybcio@kernel.org>
14 domains on Qualcomm SoCs.
17 include/dt-bindings/clock/qcom,qcm2290-gpucc.h
21 const: qcom,qcm2290-gpucc
28 - description: AHB interface clock,
29 - description: SoC CXO clock
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Dqcom,sm8450-camcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
11 - Jagadeesh Kona <quic_jkona@quicinc.com>
15 domains on SM8450.
18 include/dt-bindings/clock/qcom,sc8280xp-camcc.h
19 include/dt-bindings/clock/qcom,sm8450-camcc.h
20 include/dt-bindings/clock/qcom,sm8550-camcc.h
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Dqcom,camcc-sm8250.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,camcc-sm8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Marek <jonathan@marek.ca>
14 power domains on SM8250.
16 See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h
19 - $ref: qcom,gcc.yaml#
23 const: qcom,sm8250-camcc
27 - description: AHB
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Dqcom,dispcc-sm6125.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Martin Botka <martin.botka@somainline.org>
13 Qualcomm display clock control module provides the clocks and power domains
16 See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h
21 - qcom,sm6125-dispcc
25 - description: Board XO source
26 - description: Byte clock from DSI PHY0
[all …]
Dqcom,sm8450-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
14 domains on SM8450.
16 See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h
21 - qcom,sm8450-dispcc
26 - description: Board XO source
27 - description: Board Always On XO source
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Dqcom,videocc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <quic_tdas@quicinc.com>
14 domains on Qualcomm SoCs.
17 include/dt-bindings/clock/qcom,videocc-sc7180.h
18 include/dt-bindings/clock/qcom,videocc-sc7280.h
19 include/dt-bindings/clock/qcom,videocc-sdm845.h
20 include/dt-bindings/clock/qcom,videocc-sm8150.h
21 include/dt-bindings/clock/qcom,videocc-sm8250.h
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Dqcom,dispcc-sm8x50.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Marek <jonathan@marek.ca>
14 domains on SM8150/SM8250/SM8350.
17 include/dt-bindings/clock/qcom,dispcc-sm8150.h
18 include/dt-bindings/clock/qcom,dispcc-sm8250.h
19 include/dt-bindings/clock/qcom,dispcc-sm8350.h
24 - qcom,sc8180x-dispcc
[all …]
Dqcom,sm8550-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 domains on SM8550.
18 - include/dt-bindings/clock/qcom,sm8550-dispcc.h
19 - include/dt-bindings/clock/qcom,sm8650-dispcc.h
20 - include/dt-bindings/clock/qcom,x1e80100-dispcc.h
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/Documentation/devicetree/bindings/media/
Dnxp,dw100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xavier Roumegue <xavier.roumegue@oss.nxp.com>
12 description: |-
13 The Dewarp Engine provides high-performance dewarp processing for the
15 and wide angle lenses. It is implemented with a line/tile-cache based
24 - nxp,imx8mp-dw100
34 - description: The AXI clock
35 - description: The AHB clock
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/Documentation/devicetree/bindings/interconnect/
Dqcom,msm8996.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm MSM8996 Network-On-Chip interconnect
10 - Konrad Dybcio <konradybcio@kernel.org>
19 - qcom,msm8996-a0noc
20 - qcom,msm8996-a1noc
21 - qcom,msm8996-a2noc
22 - qcom,msm8996-bimc
23 - qcom,msm8996-cnoc
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/Documentation/devicetree/bindings/arm/apple/
Dapple,pmgr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
15 performance features. This node represents the PMGR as a syscon,
16 with sub-nodes representing individual features.
20 pattern: "^power-management@[0-9a-f]+$"
24 - enum:
25 - apple,t8103-pmgr
26 - apple,t8112-pmgr
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