Searched full:peripheral (Results 1 – 25 of 614) sorted by relevance
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| /Documentation/driver-api/memory-devices/ |
| D | ti-gpmc.rst | 24 functioning of the peripheral, while peripheral has another set of
25 timings. To have peripheral work with gpmc, peripheral timings has to
27 translated depends on the connected peripheral. Also there is a
32 from gpmc peripheral timings. struct gpmc_device_timings fields has to
33 be updated with timings from the datasheet of the peripheral that is
34 connected to gpmc. A few of the peripheral timings can be fed either
37 happen that timing as specified by peripheral datasheet is not present
38 in timing structure, in this scenario, try to correlate peripheral
40 field as required by peripheral, educate generic timing routine to
42 Then there may be cases where peripheral datasheet doesn't mention
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| /Documentation/ABI/testing/ |
| D | sysfs-platform-renesas_usb3 | 11 - "host" - switching mode from peripheral to host.
12 - "peripheral" - switching mode from host to peripheral.
17 - "peripheral" - The mode is peripheral now.
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| D | sysfs-platform-phy-rcar-gen3-usb2 | 11 - "host" - switching mode from peripheral to host.
12 - "peripheral" - switching mode from host to peripheral.
17 - "peripheral" - The mode is peripheral now.
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| /Documentation/devicetree/bindings/clock/ |
| D | pistachio-clock.txt | 4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
44 Peripheral clock controller:
47 The peripheral clock controller generates clocks for the DDR, ROM, and other
48 peripherals. The peripheral system clock ("periph_sys") generated by the core
49 clock controller is the input clock to the peripheral clock controller.
53 - reg: Must contain the base address and length of the peripheral clock
58 - clock-names: Must include "periph_sys", the peripheral system clock generated
71 Peripheral general control:
74 The peripheral general control block generates system interface clocks and
75 resets for various peripherals. It also contains miscellaneous peripheral
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| D | mvebu-gated-clock.txt | 4 peripheral clocks to be gated to save some power. The clock consumer
11 ID Clock Peripheral
28 ID Clock Peripheral
55 ID Clock Peripheral
82 ID Clock Peripheral
96 ID Clock Peripheral
123 ID Clock Peripheral
133 ID Clock Peripheral
149 22 pdma Peripheral DMA
156 ID Clock Peripheral
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| D | armada3700-periph-clock.txt | 1 * Peripheral Clock bindings for Marvell Armada 37xx SoCs
3 Marvell Armada 37xx SoCs provide peripheral clocks which are
4 used as clock source for the peripheral of the SoC.
9 The peripheral clock consumer should specify the desired clock by
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| /Documentation/devicetree/bindings/display/ |
| D | mipi-dsi-bus.txt | 15 The following assumes that only a single peripheral is connected to a DSI
34 conjunction with another DSI host to drive the same peripheral. Hardware
39 DSI peripheral
52 - reg: The virtual channel number of a DSI peripheral. Must be in the range
58 that the peripheral responds to.
59 - If the virtual channels that a peripheral responds to are consecutive, the
79 connected to this peripheral. Each DSI host's output endpoint can be linked to
80 an input endpoint of the DSI peripheral.
87 - (1), (2) and (3) are examples of a DSI host and peripheral on the DSI bus
89 - (4) is an example of a peripheral on a I2C control bus connected to a
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | mc-peripheral-props.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml#
7 title: Peripheral-specific properties for a Memory Controller bus.
10 Many Memory Controllers need to add properties to peripheral devices.
13 to be defined in the peripheral node because they are per-peripheral
38 - $ref: intel,ixp4xx-expansion-peripheral-props.yaml#
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | img,pdc-intc.txt | 27 shared SysWake interrupt, and remaining specifies shall be PDC peripheral
35 0-7: Peripheral interrupts
39 flags as follows (only 4 valid for peripheral interrupts):
74 <30 4 /* level */>, /* Peripheral 0 (RTC) */
75 <29 4 /* level */>, /* Peripheral 1 (IR) */
76 <31 4 /* level */>; /* Peripheral 2 (WDT) */
82 * An SoC peripheral that is wired through the PDC.
88 // Interrupt source Peripheral 0
89 interrupts = <0 /* Peripheral 0 (RTC) */
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| /Documentation/devicetree/bindings/iommu/ |
| D | samsung,sysmmu.yaml | 14 physical memory chunks visible as a contiguous region to DMA-capable peripheral
23 System MMUs are in many to one relation with peripheral devices, i.e. single
24 peripheral device might have multiple System MMUs (usually one for each bus
25 master), but one System MMU can handle transactions from only one peripheral
26 device. The relation between a System MMU and the peripheral device needs to be
27 defined in device node of the peripheral device.
37 For information on assigning System MMU controller to its peripheral devices,
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-peripheral-props.yaml | 4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
7 title: Peripheral-specific properties for a SPI bus.
10 Many SPI controllers need to add properties to peripheral devices. They could
13 need to be defined in the peripheral node because they are per-peripheral and
123 - $ref: arm,pl022-peripheral-props.yaml#
124 - $ref: cdns,qspi-nor-peripheral-props.yaml#
125 - $ref: fsl,dspi-peripheral-props.yaml#
126 - $ref: samsung,spi-peripheral-props.yaml#
127 - $ref: nvidia,tegra210-quad-peripheral-props.yaml#
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| D | fsl,dspi-peripheral-props.yaml | 4 $id: http://devicetree.org/schemas/spi/fsl,dspi-peripheral-props.yaml#
7 title: Peripheral-specific properties for Freescale DSPI controller
13 See spi-peripheral-props.yaml for more info.
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| D | samsung,spi-peripheral-props.yaml | 4 $id: http://devicetree.org/schemas/spi/samsung,spi-peripheral-props.yaml#
7 title: Peripheral-specific properties for Samsung S3C/S5P/Exynos SoC SPI controller
13 See spi-peripheral-props.yaml for more info.
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| D | cdns,qspi-nor-peripheral-props.yaml | 4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor-peripheral-props.yaml#
7 title: Peripheral-specific properties for the Cadence QSPI controller.
10 See spi-peripheral-props.yaml for more info.
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| /Documentation/devicetree/bindings/phy/ |
| D | hix5hd2-phy.txt | 11 - hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
12 - hisilicon,power-reg: offset and bit number within peripheral-syscon,
20 hisilicon,peripheral-syscon = <&peripheral_ctrl>;
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| /Documentation/devicetree/bindings/usb/ |
| D | atmel-usb.txt | 10 - clocks: Should reference the peripheral, host and system clocks
12 "ohci_clk" for the peripheral clock
37 - clocks: Should reference the peripheral and the UTMI clocks
39 "ehci_clk" for the peripheral clock
64 - clocks: Should reference the peripheral and the AHB clocks
66 "pclk" for the peripheral clock
95 - clocks: Should reference the peripheral and host clocks
97 "pclk" for the peripheral clock
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-atr.yaml | 27 addresses must be available, not used by any other peripheral. Each
28 remote peripheral is assigned an alias from the pool, and transactions to
29 that address will be forwarded to the remote peripheral, with the address
30 translated to the remote peripheral's real address. This property is not
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| /Documentation/devicetree/bindings/display/panel/ |
| D | sharp,lq101r1sx01.yaml | 17 Each of the DSI channels controls a separate DSI peripheral. The peripheral
19 peripheral and controls the device. The 'link2' property contains a phandle
20 to the peripheral driven by the second link (DSI-LINK2, right or odd).
49 phandle to the DSI peripheral on the secondary link. Note that the
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| D | jdi,lpm102a188a.yaml | 17 Each of the DSI channels controls a separate DSI peripheral. The peripheral
18 driven by the first link (DSI-LINK1) is considered the primary peripheral
20 peripheral driven by the second link (DSI-LINK2).
43 phandle to the DSI peripheral on the secondary link. Note that the
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| /Documentation/devicetree/bindings/net/can/ |
| D | st,stm32-bxcan.yaml | 24 Primary mode of the bxCAN peripheral is only relevant if the chip has
27 Not to be used if the peripheral is in single CAN configuration.
34 Secondary mode of the bxCAN peripheral is only relevant if the chip
37 Not to be used if the peripheral is in single CAN configuration.
70 secondary) in dual CAN peripheral configuration.
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| /Documentation/devicetree/bindings/dma/ |
| D | atmel-xdma.txt | 15 - bit 14: DIF, destination interface identifier, used to get the peripheral
17 - bit 30-24: PERID, peripheral identifier.
37 - bit 14: DIF, destination interface identifier, used to get the peripheral
39 - bit 30-24: PERID, peripheral identifier.
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | atmel,at91rm9200-pinctrl.yaml | 52 Each column will represent the possible peripheral of the pinctrl
58 Peripheral: 2 ( A and B)
66 For each peripheral/bank we will describe in a u32 if a pin can be
69 Let's take the pioA on peripheral B whose value is 0xffc00c3b
71 Peripheral B
142 Peripheral function
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| /Documentation/userspace-api/media/ |
| D | glossary.rst | 70 Hardware Peripheral
72 together make a larger user-facing functional peripheral. For
75 peripheral.
77 Also known as :term:`Peripheral`.
157 Peripheral
158 The same as :term:`Hardware Peripheral`.
172 **Serial Peripheral Interface Bus**
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| /Documentation/devicetree/bindings/arm/hisilicon/controller/ |
| D | hi3798cv200-perictrl.yaml | 7 title: Hisilicon Hi3798CV200 Peripheral Controller
13 The Hi3798CV200 Peripheral Controller controls peripherals, queries
46 peripheral-controller@8a20000 {
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| /Documentation/devicetree/bindings/sound/ |
| D | adi,max98363.yaml | 16 SoundWire peripheral device ID of MAX98363 is 0x3*019f836300
17 where * is the peripheral device unique ID decoded from pin.
18 It supports up to 10 peripheral devices(0x0 to 0x9).
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