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/Documentation/hwmon/
Dmp2888.rst25 - Programmable Multi-Phase up to 10 Phases.
46 - 'n' is number of configured phases (from 1 to 10);
48 - indexes 2 ... 1 + n for phases.
Dpmbus-core.rst178 support multiple phases, the phase parameter can be ignored. If the chip
179 supports multiple phases, a phase value of 0xff indicates all phases.
219 If the chip does not support multiple phases, the phase parameter is
220 ignored. Otherwise, a phase value of 0xff selects all phases.
229 not support multiple phases, the phase parameter is ignored. Otherwise, a phase
230 value of 0xff selects all phases.
Dmp2975.rst60 - 'k' is number of configured phases (from 1 to 8);
63 - indexes 2*n+1 ... 2*n + k for phases.
Dmax15301.rst82 temp1_input Measured maximum temperature of all phases.
Dstpddc60.rst85 temp1_input Measured maximum temperature of all phases.
Dmax16601.rst94 'N' is the number of enabled/populated phases.
Dtps53679.rst64 output channels and up to 8 phases per channel.
/Documentation/driver-api/pm/
Ddevices.rst134 they are called in phases for every device, respecting the parent-child
266 System Power Management Phases
269 Suspending or resuming the system is done in several phases. Different phases
274 callbacks. The various phases always run after tasks have been frozen and
275 before they are unfrozen. Furthermore, the ``*_noirq`` phases run at a time
279 All phases use PM domain, bus, type, class or driver callbacks (that is, methods
316 the phases are: ``prepare``, ``suspend``, ``suspend_late``, ``suspend_noirq``.
323 suspend-related phases, during the ``prepare`` phase the device
342 ``suspend_noirq`` phases as well as all of the corresponding phases of
389 "quiesce device" and "save device state" phases, in which cases
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/Documentation/devicetree/bindings/mmc/
Drockchip-dw-mshc.yaml74 to control the clock phases, "ciu-sample" is required for tuning
87 low speeds or in case where all phases work at tuning time.
90 rockchip,desired-num-phases:
/Documentation/devicetree/bindings/watchdog/
Drealtek,otto-wdt.yaml13 The timer has two timeout phases. Both phases have a maximum duration of 32
Dstarfive,jh7100-wdt.yaml16 timeout phases. At the first phase, the signal of watchdog interrupt
/Documentation/devicetree/bindings/iio/proximity/
Dsemtech,sx9360.yaml42 Capacitance measurement resolution. For both phases, "reference" and
52 PROXRAW filter strength for both phases. A value of 0 represents off,
/Documentation/ABI/testing/
Dsysfs-bus-iio-sx932414 The sensor rotates measurement across 4 phases
/Documentation/power/
Dpci.rst431 management callbacks for this purpose. They are executed in phases such that
433 belonging to the given subsystem before the next phase begins. These phases
440 be preserved, such as one of the ACPI sleep states S1-S3, the phases are:
444 The following PCI bus type's callbacks, respectively, are used in these phases::
509 S1-S3, into the working state (ACPI S0), the phases are:
514 phases::
562 to be free) in the following three phases:
573 The other two phases, however, are different.
591 back to the fully functional state and this is done in the following phases:
617 three phases:
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Dsuspend-and-interrupts.rst38 suspend-resume cycle, including the "noirq" phases of suspending and resuming
/Documentation/devicetree/bindings/timer/
Drenesas,rz-mtu3.yaml42 negative signals in six phases (12 phases in total) can be output in
91 waveforms (12 phases in total) with dead time can be output by
/Documentation/crypto/
Dintro.rst57 following phases that are reflected in the API calls applicable to such
/Documentation/driver-api/driver-model/
Doverview.rst69 The above abstraction prevents unnecessary pain during transitional phases.
/Documentation/admin-guide/pm/
Dsuspend-flows.rst79 Devices are suspended in four phases called *prepare*, *suspend*,
139 Devices are resumed in four phases called *noirq resume*, *early resume*,
Dintel_uncore_frequency_scaling.rst25 different core and uncore performance at distinct phases and they may want to
/Documentation/admin-guide/mm/
Dmemory-hotplug.rst53 Phases of Memory Hotplug
56 Memory hotplug consists of two phases:
70 Phases of Memory Hotunplug
73 Memory hotunplug consists of two phases:
/Documentation/devicetree/bindings/power/supply/
Drohm,bd99954.yaml32 # The BD99954 data sheet divides charging to three phases.
/Documentation/userspace-api/media/v4l/
Dpixfmt-srggb8-pisp-comp.rst38 Each block of 8 pixels is separated into even and odd phases of 4 pixels,
/Documentation/timers/
Dtimekeeping.rst41 the counter register is read in two phases on the bus lowest 16 bits first
/Documentation/filesystems/
Dsharedsubtree.rst954 The overall algorithm breaks the operation into 3 phases: (look at
958 2. commit phases.
959 3. abort phases.

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