| /Documentation/translations/zh_CN/driver-api/phy/ |
| D | phy.rst | 4 :Original: Documentation/driver-api/phy/phy.rst
16 本文档解释了 PHY 的通用框架和提供的API，以及使用方法。
21 *PHY* 是物理层的缩写，它被用来把设备连接到一个物理媒介，例如USB控制器
22 有一个提供序列化、反序列化、编码、解码和负责获取所需的数据传输速率的 PHY。
23 注意，有些USB控制器内嵌了 PHY 的功能，其它的则使用了一个外置的PHY，此外
24 使用 PHY 的设备还有无线网、以太网、SATA等（控制器）。
26 创建这个框架的目的是将遍布 Linux 内核的 PHY 驱动程序融入到 drivers/phy，
29 该框架仅适用于使用外部 PHY（PHY 功能未嵌入控制器内）的设备。
34 PHY provider是指实现一个或多个 PHY 实例的实体。对于 PHY provider 仅
35 实现单个 PHY 实例的简单情况，框架在 of_phy_simple_xlate 中提供其自己
[all …]
|
| /Documentation/driver-api/phy/ |
| D | phy.rst | 2 PHY subsystem
7 This document explains the Generic PHY Framework along with the APIs provided,
13 *PHY* is the abbreviation for physical layer. It is used to connect a device
14 to the physical medium e.g., the USB controller has a PHY to provide functions
17 controllers have PHY functionality embedded into it and others use an external
18 PHY. Other peripherals that use PHY include Wireless LAN, Ethernet,
21 The intention of creating this framework is to bring the PHY drivers spread
22 all over the Linux kernel to drivers/phy to increase code re-use and for
25 This framework will be of use only to devices that use external PHY (PHY
28 Registering/Unregistering the PHY provider
[all …]
|
| /Documentation/devicetree/bindings/phy/ |
| D | qcom,sc8280xp-qmp-ufs-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml#
7 title: Qualcomm QMP PHY controller (UFS, SC8280XP)
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,msm8996-qmp-ufs-phy
20 - qcom,msm8998-qmp-ufs-phy
21 - qcom,sa8775p-qmp-ufs-phy
22 - qcom,sc7180-qmp-ufs-phy
23 - qcom,sc7280-qmp-ufs-phy
24 - qcom,sc8180x-qmp-ufs-phy
25 - qcom,sc8280xp-qmp-ufs-phy
[all …]
|
| D | qcom,sc8280xp-qmp-pcie-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
21 - qcom,sc8180x-qmp-pcie-phy
22 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
23 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
24 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
25 - qcom,sdm845-qhp-pcie-phy
[all …]
|
| D | brcm,stingray-usb-phy.txt | 1 Broadcom Stingray USB PHY
5 - "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
6 - "brcm,sr-usb-hs-phy" is a single HS PHY.
7 - reg: offset and length of the PHY blocks registers
8 - #phy-cells:
9 - Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate
10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
11 - Must be 0 for brcm,sr-usb-hs-phy.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties
16 usbphy0: usb-phy@0 {
[all …]
|
| D | qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml#
7 title: Qualcomm QMP PHY controller (USB, SC8280XP)
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,ipq6018-qmp-usb3-phy
20 - qcom,ipq8074-qmp-usb3-phy
21 - qcom,ipq9574-qmp-usb3-phy
22 - qcom,msm8996-qmp-usb3-phy
23 - qcom,qdu1000-qmp-usb3-uni-phy
24 - qcom,sa8775p-qmp-usb3-uni-phy
25 - qcom,sc8180x-qmp-usb3-uni-phy
[all …]
|
| D | phy-bindings.txt | 2 information about PHY subsystem refer to Documentation/driver-api/phy/phy.rst
4 PHY device node
8 #phy-cells: Number of cells in a PHY specifier; The meaning of all those
9 cells is defined by the binding for the phy node. The PHY
11 PHY.
14 phy-supply: Phandle to a regulator that provides power to the PHY. This
15 regulator will be managed during the PHY power on/off sequence.
19 phys: phy {
24 #phy-cells = <1>;
29 That node describes an IP block (PHY provider) that implements 2 different PHYs.
[all …]
|
| D | mediatek,mt8365-csi-rx.yaml | 5 $id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#
8 title: Mediatek Sensor Interface MIPI CSI CD-PHY
15 The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2
17 Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only
31 '#phy-cells':
34 If the PHY doesn't support mode selection then #phy-cells must be 0 and
35 PHY mode is described using phy-type property.
36 If the PHY supports mode selection, then #phy-cells must be 1 and mode
37 is set in the PHY cells. Supported modes are:
40 See include/dt-bindings/phy/phy.h for constants.
[all …]
|
| D | samsung,usb3-drd-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
7 title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
15 For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
16 compatible PHYs, the second cell in the PHY specifier identifies the
17 PHY id, which is interpreted as follows::
18 0 - UTMI+ type phy,
19 1 - PIPE3 type phy.
21 For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
28 - google,gs101-usb31drd-phy
29 - samsung,exynos5250-usbdrd-phy
[all …]
|
| D | phy-hisi-inno-usb2.txt | 1 Device tree bindings for HiSilicon INNO USB2 PHY
5 "hisilicon,inno-usb2-phy",
6 "hisilicon,hi3798cv200-usb2-phy".
7 - reg: Should be the address space for PHY configuration register in peripheral
9 - clocks: The phandle and clock specifier pair for INNO USB2 PHY device
11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
16 The INNO USB2 PHY device should be a child node of peripheral controller that
17 contains the PHY configuration register, and each device supports up to 2 PHY
18 ports which are represented as child nodes of INNO USB2 PHY device.
20 Required properties for PHY port node:
[all …]
|
| D | renesas,usb2-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/renesas,usb2-phy.yaml#
7 title: Renesas R-Car generation 3 USB 2.0 PHY
17 - renesas,usb2-phy-r8a77470 # RZ/G1C
18 - renesas,usb2-phy-r9a08g045 # RZ/G3S
22 - renesas,usb2-phy-r7s9210 # RZ/A2
23 - renesas,usb2-phy-r8a774a1 # RZ/G2M
24 - renesas,usb2-phy-r8a774b1 # RZ/G2N
25 - renesas,usb2-phy-r8a774c0 # RZ/G2E
26 - renesas,usb2-phy-r8a774e1 # RZ/G2H
27 - renesas,usb2-phy-r8a7795 # R-Car H3
[all …]
|
| D | qcom,sc8280xp-qmp-usb43dp-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
7 title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,sc7180-qmp-usb3-dp-phy
20 - qcom,sc7280-qmp-usb3-dp-phy
21 - qcom,sc8180x-qmp-usb3-dp-phy
22 - qcom,sc8280xp-qmp-usb43dp-phy
23 - qcom,sdm845-qmp-usb3-dp-phy
24 - qcom,sm6350-qmp-usb3-dp-phy
25 - qcom,sm8150-qmp-usb3-dp-phy
[all …]
|
| D | brcm,sata-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#
7 title: Broadcom SATA3 PHY
14 pattern: "^sata[-|_]phy(@.*)?$"
20 - brcm,bcm7216-sata-phy
21 - brcm,bcm7425-sata-phy
22 - brcm,bcm7445-sata-phy
23 - brcm,bcm63138-sata-phy
24 - const: brcm,phy-sata3
26 - const: brcm,iproc-nsp-sata-phy
28 - const: brcm,iproc-ns2-sata-phy
[all …]
|
| D | realtek,usb2phy.yaml | 5 $id: http://devicetree.org/schemas/phy/realtek,usb2phy.yaml#
8 title: Realtek DHC SoCs USB 2.0 PHY
14 Realtek USB 2.0 PHY support the digital home center (DHC) RTD series SoCs.
15 The USB 2.0 PHY driver is designed to support the XHCI controller. The SoCs
16 support multiple XHCI controllers. One PHY device node maps to one XHCI
21 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some
23 XHCI controller#0 -- usb2phy -- phy#0
24 |- usb3phy -- phy#0
25 XHCI controller#1 -- usb2phy -- phy#0
26 XHCI controller#2 -- usb2phy -- phy#0
[all …]
|
| D | allwinner,sun9i-a80-usb-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml#
7 title: Allwinner A80 USB PHY
14 "#phy-cells":
18 const: allwinner,sun9i-a80-usb-phy
26 description: Main PHY Clock
29 - description: Main PHY clock
35 - const: phy
38 - const: phy
45 - description: Normal USB PHY reset
51 - const: phy
[all …]
|
| D | ti-phy.txt | 1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
3 OMAP CONTROL PHY
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
11 e.g. USB3 PHY and SATA PHY on OMAP5.
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
14 e.g. PCIE PHY in DRA7x
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
[all …]
|
| D | socionext,uniphier-usb2-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb2-phy.yaml#
7 title: Socionext UniPhier USB2 PHY
10 This describes the devicetree bindings for PHY interface built into
13 controller doesn't include its own High-Speed PHY. This needs to specify
14 USB2 PHY instead of USB3 HS-PHY.
22 - socionext,uniphier-pro4-usb2-phy
23 - socionext,uniphier-ld11-usb2-phy
32 "^phy@[0-9]+$":
41 The ID number for the PHY
43 "#phy-cells":
[all …]
|
| D | renesas,rcar-gen2-usb-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/renesas,rcar-gen2-usb-phy.yaml#
7 title: Renesas R-Car Gen2 USB PHY
16 - renesas,usb-phy-r8a7742 # RZ/G1H
17 - renesas,usb-phy-r8a7743 # RZ/G1M
18 - renesas,usb-phy-r8a7744 # RZ/G1N
19 - renesas,usb-phy-r8a7745 # RZ/G1E
20 - renesas,usb-phy-r8a77470 # RZ/G1C
21 - renesas,usb-phy-r8a7790 # R-Car H2
22 - renesas,usb-phy-r8a7791 # R-Car M2-W
23 - renesas,usb-phy-r8a7794 # R-Car E2
[all …]
|
| D | qcom,qusb2-phy.yaml | 5 $id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#
8 title: Qualcomm QUSB2 phy controller
21 - qcom,ipq6018-qusb2-phy
22 - qcom,ipq8074-qusb2-phy
23 - qcom,ipq9574-qusb2-phy
24 - qcom,msm8953-qusb2-phy
25 - qcom,msm8996-qusb2-phy
26 - qcom,msm8998-qusb2-phy
27 - qcom,qcm2290-qusb2-phy
28 - qcom,sdm660-qusb2-phy
[all …]
|
| D | brcm,brcmstb-usb-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/brcm,brcmstb-usb-phy.yaml#
7 title: Broadcom STB USB PHY
9 description: Broadcom's PHY that handles EHCI/OHCI and/or XHCI
18 - brcm,bcm4908-usb-phy
19 - brcm,bcm7211-usb-phy
20 - brcm,bcm7216-usb-phy
21 - brcm,brcmstb-usb-phy
29 - description: USB PHY register
75 description: PHY Device mode. If this property is not defined, the PHY will
88 description: Indicates the PHY has an XHCI PHY.
[all …]
|
| D | lantiq,vrx200-pcie-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
7 title: Lantiq VRX200 and ARX300 PCIe PHY
13 "#phy-cells":
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19 - lantiq,vrx200-pcie-phy
20 - lantiq,arx300-pcie-phy
27 - description: PHY module clock
32 - const: phy
37 - description: exclusive PHY reset line
38 - description: shared reset line between the PCIe PHY and PCIe controller
[all …]
|
| D | samsung,usb2-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/samsung,usb2-phy.yaml#
7 title: Samsung S5P/Exynos SoC USB 2.0 PHY
15 The first phandle argument in the PHY specifier identifies the PHY, its
22 Exynos3250 has only USB device phy available as phy 0.
30 - samsung,exynos3250-usb2-phy
31 - samsung,exynos4210-usb2-phy
32 - samsung,exynos4x12-usb2-phy
33 - samsung,exynos5250-usb2-phy
34 - samsung,exynos5420-usb2-phy
35 - samsung,s5pv210-usb2-phy
[all …]
|
| /Documentation/devicetree/bindings/net/ |
| D | realtek,rtl82xx.yaml | 7 title: Realtek RTL82xx PHY
20 - ethernet-phy-id001c.c800
21 - ethernet-phy-id001c.c816
22 - ethernet-phy-id001c.c838
23 - ethernet-phy-id001c.c840
24 - ethernet-phy-id001c.c848
25 - ethernet-phy-id001c.c849
26 - ethernet-phy-id001c.c84a
27 - ethernet-phy-id001c.c862
28 - ethernet-phy-id001c.c878
[all …]
|
| D | nxp,tja11xx.yaml | 7 title: NXP TJA11xx PHY
20 - ethernet-phy-id0180.dc40
21 - ethernet-phy-id0180.dc41
22 - ethernet-phy-id0180.dc48
23 - ethernet-phy-id0180.dd00
24 - ethernet-phy-id0180.dd01
25 - ethernet-phy-id0180.dd02
26 - ethernet-phy-id0180.dc80
27 - ethernet-phy-id0180.dc82
28 - ethernet-phy-id001b.b010
[all …]
|
| D | ethernet-phy-package.yaml | 4 $id: http://devicetree.org/schemas/net/ethernet-phy-package.yaml#
7 title: Ethernet PHY Package Common Properties
13 PHY packages are multi-port Ethernet PHY of the same family
14 and each Ethernet PHY is affected by the global configuration
15 of the PHY package.
17 Each reg of the PHYs defined in the PHY package node is
18 absolute and describe the real address of the Ethernet PHY on
23 pattern: "^ethernet-phy-package@[a-f0-9]+$"
29 The base ID number for the PHY package.
30 Commonly the ID of the first PHY in the PHY package.
[all …]
|