Searched full:phy0 (Results 1 – 25 of 59) sorted by relevance
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| /Documentation/devicetree/bindings/usb/ |
| D | amlogic,meson-g12a-usb-ctrl.yaml | 113 - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used
115 - const: usb3-phy0 # USB3 PHY if USB3_0 is used
132 - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used
152 - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used
214 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
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| /Documentation/devicetree/bindings/clock/ |
| D | qcom,sm8450-dispcc.yaml | 30 - description: Byte clock from DSI PHY0
31 - description: Pixel clock from DSI PHY0
34 - description: Link clock from DP PHY0
35 - description: VCO DIV clock from DP PHY0
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| D | qcom,sm8550-dispcc.yaml | 35 - description: Byte clock from DSI PHY0
36 - description: Pixel clock from DSI PHY0
39 - description: Link clock from DP PHY0
40 - description: VCO DIV clock from DP PHY0
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| D | qcom,sm6115-dispcc.yaml | 27 - description: Byte clock from DSI PHY0
28 - description: Pixel clock from DSI PHY0
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| D | qcom,sm4450-dispcc.yaml | 32 - description: Byte clock from DSI PHY0
33 - description: Pixel clock from DSI PHY0
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| D | qcom,gcc-msm8953.yaml | 27 - description: Byte clock from DSI PHY0
28 - description: Pixel clock from DSI PHY0
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| D | qcom,gcc-msm8976.yaml | 29 - description: Pixel clock from DSI PHY0
30 - description: Byte clock from DSI PHY0
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| D | qcom,sm7150-dispcc.yaml | 30 - description: Byte clock from MDSS DSI PHY0
31 - description: Pixel clock from MDSS DSI PHY0
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| D | qcom,sdm845-dispcc.yaml | 30 - description: Byte clock from DSI PHY0
31 - description: Pixel clock from DSI PHY0
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| D | qcom,dispcc-sm6125.yaml | 26 - description: Byte clock from DSI PHY0
27 - description: Pixel clock from DSI PHY0
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| D | qcom,dispcc-sm8x50.yaml | 33 - description: Byte clock from DSI PHY0
34 - description: Pixel clock from DSI PHY0
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| /Documentation/devicetree/bindings/net/ |
| D | qcom-emac.txt | 48 phy-handle = <&phy0>;
52 phy0: ethernet-phy@0 {
97 phy-handle = <&phy0>;
101 phy0: ethernet-phy@4 {
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| D | toshiba,visconti-dwmac.yaml | 73 phy-handle = <&phy0>;
80 phy0: ethernet-phy@1 {
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| D | rockchip,emac.yaml | 103 phy = <&phy0>;
111 phy0: ethernet-phy@0 {
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| D | hisilicon-hip04-net.txt | 37 phy0: ethernet-phy@0 {
69 phy-handle = <&phy0>;
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| D | loongson,ls1c-emac.yaml | 100 phy-handle = <&phy0>;
109 phy0: ethernet-phy@13 {
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| D | loongson,ls1b-gmac.yaml | 101 phy-handle = <&phy0>;
110 phy0: ethernet-phy@0 {
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| D | engleder,tsnep.yaml | 88 phy-handle = <&phy0>;
93 phy0: ethernet-phy@1 {
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| D | hisilicon-femac-mdio.txt | 19 phy0: phy@1 {
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| D | brcm,asp-v2.0.yaml | 124 phy0: ethernet-phy@1 {
149 phy-handle = <&phy0>;
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| D | brcm,bcmgenet.yaml | 123 phy-handle = <&phy0>;
137 phy0: ethernet-phy@0 {
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| D | cortina,gemini-ethernet.yaml | 93 phy0: ethernet-phy@1 {
123 phy-handle = <&phy0>;
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| D | starfive,jh7110-dwmac.yaml | 172 phy-handle = <&phy0>;
179 phy0: ethernet-phy@0 {
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| /Documentation/devicetree/bindings/phy/ |
| D | nvidia,tegra20-usb-phy.yaml | 32 PHY0 and PHY2 share power and ground, PHY0 contains shared registers.
33 PHY0 and PHY2 must specify two register sets, where the first set is
34 PHY own registers and the second set is the PHY0 registers.
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | lantiq,gswip.yaml | 117 phy-handle = <&phy0>;
165 phy0: ethernet-phy@0 {
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