Searched full:phy2 (Results 1 – 23 of 23) sorted by relevance
| /Documentation/firmware-guide/acpi/dsd/ |
| D | phy.rst | 38 Device(PHY2) {
40 } // end of PHY2
99 The PHY1 and PHY2 nodes represent the PHYs connected to MDIO bus MDI0
110 Device(PHY2) {
112 } // end of PHY2
141 Package (2) {"phy-handle", \_SB.MDI0.PHY2}}
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| /Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx8mp-hsio-blk-ctrl.yaml | 38 - const: usb-phy2
89 "usb-phy2", "pcie", "pcie-phy";
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| /Documentation/devicetree/bindings/clock/ |
| D | qcom,sm8450-dispcc.yaml | 38 - description: Link clock from DP PHY2
39 - description: VCO DIV clock from DP PHY2
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| D | qcom,sm8550-dispcc.yaml | 43 - description: Link clock from DP PHY2
44 - description: VCO DIV clock from DP PHY2
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| D | qcom,ipq9574-gcc.yaml | 32 - description: PCIE30 PHY2 pipe clock source
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| /Documentation/devicetree/bindings/ata/ |
| D | apm-xgene.txt | 39 phy2: phy@1f22a000 {
61 phys = <&phy2 0>;
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| /Documentation/devicetree/bindings/net/ |
| D | hisilicon-hix5hd2-gmac.txt | 49 phy-handle = <&phy2>;
57 phy2: ethernet-phy@2 {
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| D | intel,ixp4xx-ethernet.yaml | 97 phy-handle = <&phy2>;
105 phy2: ethernet-phy@2 {
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| D | snps,dwc-qos-ethernet.txt | 145 phy-handle = <&phy2>;
162 phy2: phy@1 {
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| D | cavium-pip.txt | 64 phy-handle = <&phy2>;
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| /Documentation/devicetree/bindings/usb/ |
| D | amlogic,meson-g12a-usb-ctrl.yaml | 154 - const: usb2-phy2 # USB2 PHY2 if USBOTG_C port is used
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| D | ti,am62-usb.yaml | 20 - description: USB PHY2 register space
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| /Documentation/devicetree/bindings/phy/ |
| D | ti,omap-usb2.yaml | 19 - ti,dra7x-usb2-phy2
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| D | nvidia,tegra20-usb-phy.yaml | 32 PHY0 and PHY2 share power and ground, PHY0 contains shared registers.
33 PHY0 and PHY2 must specify two register sets, where the first set is
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| D | apm-xgene-phy.txt | 66 phy2: phy@1f22a000 {
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | hirschmann,hellcreek.yaml | 112 phy-handle = <&phy2>;
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| D | mscc,ocelot.yaml | 127 phy-handle = <&phy2>;
196 phy-handle = <&phy2>;
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| D | marvell,mv88e6xxx.yaml | 250 phy2: ethernet-phy@c {
331 phy-handle = <&phy2>;
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| D | realtek.yaml | 182 phy-handle = <&phy2>;
220 phy2: ethernet-phy@2 {
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-stp-xway.yaml | 97 lantiq,phy2 = <0x7>;
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| /Documentation/devicetree/bindings/scsi/ |
| D | hisilicon-sas.txt | 79 <279 4>,<283 4>,<284 4>,/* phy2 */
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| /Documentation/devicetree/bindings/pci/ |
| D | mediatek,mt7621-pcie.yaml | 173 phy-names = "pcie-phy2";
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| D | mediatek-pcie.txt | 111 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
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