Searched full:pic (Results 1 – 25 of 38) sorted by relevance
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | open-pic.txt | 1 * Open PIC Binding
4 representation of an Open PIC compliant interrupt controller. This binding is
5 based on the binding defined for Open PIC in [1] and is a superset of that
13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
20 as an Open PIC. No property value shall be defined.
31 - pic-no-reset: The presence of this property indicates that the PIC
55 * An Open PIC interrupt controller
57 mpic: pic@40000 {
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| D | loongson,pch-pic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#
7 title: Loongson PCH PIC Controller
19 const: loongson,pch-pic-1.0
24 loongson,pic-base-vec:
27 to PCH PIC.
40 - loongson,pic-base-vec
49 pic: interrupt-controller@10000000 {
50 compatible = "loongson,pch-pic-1.0";
54 loongson,pic-base-vec = <64>;
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| D | opencores,or1k-pic.txt | 5 - compatible : should be "opencores,or1k-pic-level" for variants with
6 level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
7 edge triggered interrupt lines or "opencores,or1200-pic" for machines
10 "opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
20 compatible = "opencores,or1k-pic-level";
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| D | marvell,armada-8k-pic.txt | 1 Marvell Armada 7K/8K PIC Interrupt controller
4 This is the Device Tree binding for the PIC, a secondary interrupt
9 - compatible: should be "marvell,armada-8k-pic"
13 - reg: the register area for the PIC interrupt controller
19 pic: interrupt-controller@3f0100 {
20 compatible = "marvell,armada-8k-pic";
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| D | cdns,xtensa-pic.txt | 1 * Xtensa built-in Programmable Interrupt Controller (PIC)
4 - compatible: Should be "cdns,xtensa-pic".
17 pic: pic {
18 compatible = "cdns,xtensa-pic";
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| D | cdns,xtensa-mx.txt | 6 Remaining properties have exact same meaning as in Xtensa PIC
7 (see cdns,xtensa-pic.txt).
10 pic: pic {
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| D | google,goldfish-pic.txt | 1 Android Goldfish PIC
8 - compatible : should contain "google,goldfish-pic"
22 compatible = "google,goldfish-pic";
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| D | idt,32434-pic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/idt,32434-pic.yaml#
20 const: idt,32434-pic
42 compatible = "idt,32434-pic";
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| D | intel,ce4100-lapic.yaml | 46 PIC Mode - Legacy external 8259 compliant PIC interrupt controller.
50 For OF based systems, it is by default set to PIC mode.
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| D | arm,versatile-fpga-irq.txt | 26 pic: pic@14000000 {
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| D | loongson,htpic.yaml | 17 interrupts from PCH PIC connected on HyperTransport bus.
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| /Documentation/devicetree/bindings/pci/ |
| D | v3-v360epc-pci.txt | 39 interrupt-parent = <&pic>;
56 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
57 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
58 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
59 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
61 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
62 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
63 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
64 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
66 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/ |
| D | pic.txt | 4 - fsl,cpm1-pic
6 - fsl,pq1-pic
7 - fsl,cpm2-pic
17 compatible = "mpc8272-pic", "fsl,cpm2-pic";
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| D | usb.txt | 13 interrupt-parent = <&PIC>;
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| /Documentation/translations/zh_TW/arch/loongarch/ |
| D | irq-chip-model.rst | 15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片組的主中
19 全局中斷控制器（每個芯片一個，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
27 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
46 | PCH-PIC | | PCH-MSI |
63 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
77 | PCH-PIC | | PCH-MSI |
117 PCH-PIC::
156 - PCH-PIC/PCH-MSI：即《龍芯7A1000橋片用戶手冊》第5章所描述的“中斷控制器”；
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| /Documentation/translations/zh_CN/arch/loongarch/ |
| D | irq-chip-model.rst | 15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
27 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
46 | PCH-PIC | | PCH-MSI |
63 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
77 | PCH-PIC | | PCH-MSI |
95 送达CPUINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/PCH-LPC，然后由EIOINTC
109 | PCH-PIC | | PCH-MSI |
149 PCH-PIC::
188 - PCH-PIC/PCH-MSI：即《龙芯7A1000桥片用户手册》第5章所描述的“中断控制器”；
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| /Documentation/arch/loongarch/ |
| D | irq-chip-model.rst | 11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
43 | PCH-PIC | | PCH-MSI |
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
75 | PCH-PIC | | PCH-MSI |
94 go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly::
107 | PCH-PIC | | PCH-MSI |
147 PCH-PIC::
189 - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
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| /Documentation/devicetree/bindings/ |
| D | incomplete-devices.yaml | 161 - CBEA,platform-open-pic
162 - CBEA,platform-spider-pic
183 - nintendo,flipper-pic
185 - nintendo,hollywood-pic
202 - sti,platform-spider-pic
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| /Documentation/devicetree/bindings/gpio/ |
| D | idt,32434-gpio.yaml | 22 - const: pic
55 reg-names = "gpio", "pic";
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| /Documentation/devicetree/bindings/powerpc/nintendo/ |
| D | wii.txt | 53 - compatible : should be "nintendo,flipper-pic"
137 - compatible : should be "nintendo,hollywood-pic"
140 - interrupts : should contain the cascade interrupt of the "flipper" pic
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic.txt | 7 and QorIQ processors and is compatible with the Open PIC. The
8 notable difference from Open PIC binding is the addition of 2
47 - pic-no-reset
152 mpic: pic@40000 {
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| D | mpc5200.txt | 77 interrupt-controller@<addr> fsl,mpc5200-pic need an interrupt
170 Interrupt controller (fsl,mpc5200-pic) node
172 The mpc5200 pic binding splits hardware IRQ numbers into two levels. The
173 split reflects the layout of the PIC hardware itself, which groups
179 The interrupts property for device nodes using the mpc5200 pic consists
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| /Documentation/arch/x86/i386/ |
| D | IO-APIC.rst | 30 2: 0 XT-PIC cascade
31 13: 1 XT-PIC fpu
39 Some interrupts are still listed as 'XT PIC', but this is not a problem;
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| /Documentation/devicetree/bindings/usb/ |
| D | maxim,max3421.txt | 21 interrupt-parent = <&PIC>;
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | serial.txt | 27 interrupt-parent = <&PIC>;
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