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/Documentation/devicetree/bindings/pinctrl/
Dsamsung,pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
19 the following format 'pinctrl{n}' where n is a unique number for the alias.
22 - External GPIO interrupts (see interrupts property in pin controller node);
24 - External wake-up interrupts - multiplexed (capable of waking up the system
[all …]
Dingenic,pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/ingenic,pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Please refer to pinctrl-bindings.txt in this directory for details of the
11 common pinctrl bindings used by client devices, including the meaning of the
28 - Paul Cercueil <paul@crapouillou.net>
33 - enum:
34 - ingenic,jz4730-pinctrl
35 - ingenic,jz4740-pinctrl
[all …]
Drockchip,pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/rockchip,pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
18 Please refer to pinctrl-bindings.txt in this directory for details of the
19 common pinctrl bindings used by client devices, including the meaning of the
26 various pad settings such as pull-up, etc.
29 defined as gpio sub-nodes of the pinmux controller.
34 - rockchip,px30-pinctrl
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Dmscc,ocelot-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
16 - microchip,lan966x-pinctrl
17 - microchip,sparx5-pinctrl
18 - mscc,jaguar2-pinctrl
19 - mscc,luton-pinctrl
[all …]
Dapple,pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/apple,pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Kettenis <kettenis@openbsd.org>
20 - enum:
21 - apple,t8103-pinctrl
22 - apple,t8112-pinctrl
23 - apple,t6000-pinctrl
24 - const: apple,pinctrl
[all …]
Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
[all …]
Dmediatek,mt65xx-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl
22 - mediatek,mt8127-pinctrl
[all …]
Drenesas,rzg2l-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
24 - items:
25 - enum:
26 - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
[all …]
Dpinctrl-rk805.txt3 RK805 has 2 pins which can be configured as GPIO output only.
5 Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
6 for details of the common pinctrl bindings used by client devices,
10 --------------------------
13 - pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
14 - pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
15 <pinctrl-bindings.txt>.
17 The pin configurations are defined as child of the pinctrl states node. Each
18 sub-node have following properties:
21 ------------------
[all …]
Damlogic,meson-pinctrl-a1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/amlogic,meson-pinctrl-a1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 - $ref: amlogic,meson-pinctrl-common.yaml#
18 - amlogic,c3-periphs-pinctrl
19 - amlogic,t7-periphs-pinctrl
20 - amlogic,meson-a1-periphs-pinctrl
21 - amlogic,meson-s4-periphs-pinctrl
[all …]
Dpinctrl-single.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
21 - enum:
22 - pinctrl-single
23 - pinconf-single
24 - items:
25 - enum:
[all …]
Damlogic,meson8-pinctrl-cbus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/amlogic,meson8-pinctrl-cbus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 - $ref: amlogic,meson-pinctrl-common.yaml#
18 - enum:
19 - amlogic,meson8-cbus-pinctrl
20 - amlogic,meson8b-cbus-pinctrl
21 - amlogic,meson-gxbb-periphs-pinctrl
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Damlogic,meson8-pinctrl-aobus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/amlogic,meson8-pinctrl-aobus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 - $ref: amlogic,meson-pinctrl-common.yaml#
18 - enum:
19 - amlogic,meson8-aobus-pinctrl
20 - amlogic,meson8b-aobus-pinctrl
21 - amlogic,meson-gxbb-aobus-pinctrl
[all …]
Drenesas,rza2-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
23 const: renesas,r7s9210-pinctrl # RZ/A2M
28 gpio-controller: true
30 '#gpio-cells':
[all …]
Dallwinner,sun4i-a10-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#gpio-cells":
21 "#interrupt-cells":
30 - allwinner,sun4i-a10-pinctrl
31 - allwinner,sun5i-a10s-pinctrl
[all …]
Datmel,at91rm9200-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/atmel,at91rm9200-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manikandan Muralidharan <manikandan.m@microchip.com>
22 - items:
23 - enum:
24 - atmel,at91rm9200-pinctrl
25 - atmel,at91sam9x5-pinctrl
26 - atmel,sama5d3-pinctrl
[all …]
Dpinctrl-vt8500.txt1 VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller
7 - compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl",
8 "wm8750-pinctrl" or "wm,wm8850-pinctrl"
9 - reg: Should contain the physical address of the module's registers.
10 - interrupt-controller: Marks the device node as an interrupt controller.
11 - #interrupt-cells: Should be two.
12 - gpio-controller: Marks the device node as a GPIO controller.
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 bit 0 - active low
19 Please refer to pinctrl-bindings.txt in this directory for details of the
[all …]
Dmediatek,mt8192-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8192-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
24 the amount of cells must be specified as 2. See the below mentioned gpio
26 const: 2
[all …]
Dsocionext,uniphier-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/socionext,uniphier-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Masahiro Yamada <yamada.masahiro@socionext.com>
16 - socionext,uniphier-ld4-pinctrl
17 - socionext,uniphier-pro4-pinctrl
18 - socionext,uniphier-sld8-pinctrl
19 - socionext,uniphier-pro5-pinctrl
20 - socionext,uniphier-pxs2-pinctrl
[all …]
Dstarfive,jh7110-aon-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
18 - Jianlong Huang <jianlong.huang@starfivetech.com>
22 const: starfive,jh7110-aon-pinctrl
33 interrupt-controller: true
35 '#interrupt-cells':
36 const: 2
[all …]
Dmediatek,mt6779-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Teng <andy.teng@mediatek.com>
11 - Sean Wang <sean.wang@kernel.org>
20 - mediatek,mt6779-pinctrl
21 - mediatek,mt6797-pinctrl
26 reg-names: true
28 gpio-controller: true
[all …]
Dqcom,mdm9615-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,mdm9615-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
14 $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18 const: qcom,mdm9615-pinctrl
27 "-state$":
29 - $ref: "#/$defs/qcom-mdm9615-pinctrl-state"
30 - patternProperties:
[all …]
Drenesas,rzn1-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - enum:
17 - renesas,r9a06g032-pinctrl # RZ/N1D
18 - renesas,r9a06g033-pinctrl # RZ/N1S
19 - const: renesas,rzn1-pinctrl # Generic RZ/N1
[all …]
Dfsl,scu-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,scu-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX SCU Client Device Node - Pinctrl Based on SCU Message Protocol
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 Client nodes are maintained as children of the relevant IMX-SCU device node.
14 This binding uses the i.MX common pinctrl binding.
15 (Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt)
18 - $ref: pinctrl.yaml#
[all …]
/Documentation/devicetree/bindings/pwm/
Dpwm-st.txt2 --------------------------------------
5 - compatible : "st,pwm"
6 - #pwm-cells : Number of cells used to specify a PWM. First cell
7 specifies the per-chip index of the PWM to use and the
8 second cell is the period in nanoseconds - fixed to 2
10 - reg : Physical base address and length of the controller's
12 - pinctrl-names: Set to "default".
13 - pinctrl-0: List of phandles pointing to pin configuration nodes
15 For Pinctrl properties, please refer to [1].
16 - clock-names: Valid entries are "pwm" and/or "capture".
[all …]

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