Searched +full:pinctrl +full:- +full:names (Results 1 – 25 of 417) sorted by relevance
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-cpcap-usb.txt | 4 compatible: Shall be either "motorola,cpcap-usb-phy" or
5 "motorola,mapphone-cpcap-usb-phy"
6 #phy-cells: Shall be 0
8 interrupt-names: Interrupt names
9 io-channels: IIO ADC channels used by the USB PHY
10 io-channel-names: IIO ADC channel names
11 vusb-supply: Regulator for the PHY
14 pinctrl: Optional alternate pin modes for the PHY
15 pinctrl-names: Names for optional pin modes
16 mode-gpios: Optional GPIOs for configuring alternate modes
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| D | qcom,usb-hsic-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hsic-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Vinod Koul <vkoul@kernel.org>
16 - enum:
17 - qcom,usb-hsic-phy-mdm9615
18 - qcom,usb-hsic-phy-msm8974
19 - const: qcom,usb-hsic-phy
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| /Documentation/devicetree/bindings/mmc/ |
| D | microchip,sdhci-pic32.txt | 4 and the properties used by the sdhci-pic32 driver.
7 - compatible: Should be "microchip,pic32mzda-sdhci"
8 - interrupts: Should contain interrupt
9 - clock-names: Should be "base_clk", "sys_clk".
10 See: Documentation/devicetree/bindings/resource-names.txt
11 - clocks: Phandle to the clock.
12 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
13 - pinctrl-names: A pinctrl state names "default" must be defined.
14 - pinctrl-0: Phandle referencing pin configuration of the SDHCI controller.
15 See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
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| D | sdhci-st.txt | 1 * STMicroelectronics sdhci-st MMC/SD controller
5 used by the sdhci-st driver.
8 - compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
13 - clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
14 See: Documentation/devicetree/bindings/resource-names.txt
15 - clocks: Phandle to the clock.
16 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
18 - interrupts: One mmc interrupt should be described here.
19 - interrupt-names: Should be "mmcirq".
21 - pinctrl-names: A pinctrl state names "default" must be defined.
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| /Documentation/devicetree/bindings/usb/ |
| D | ehci-st.txt | 4 - compatible : must be "st,st-ehci-300x"
5 - reg : physical base addresses of the controller and length of memory mapped
7 - interrupts : one EHCI interrupt should be described here
8 - pinctrl-names : a pinctrl state named "default" must be defined
9 - pinctrl-0 : phandle referencing pin configuration of the USB controller
10 See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
11 - clocks : phandle list of usb clocks
12 - clock-names : should be "ic" for interconnect clock and "clk48"
13 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - phys : phandle for the PHY device
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| D | dwc3-st.txt | 3 This file documents the parameters for the dwc3-st driver.
8 - compatible : must be "st,stih407-dwc3"
9 - reg : glue logic base address and USB syscfg ctrl register offset
10 - reg-names : should be "reg-glue" and "syscfg-reg"
11 - st,syscon : should be phandle to system configuration node which
13 - resets : list of phandle and reset specifier pairs. There should be two entries, one
15 - reset-names : list of reset signal names. Names should be "powerdown" and "softreset"
16 See: Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml
19 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
22 - pinctl-names : A pinctrl state named "default" must be defined
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-mux-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mux-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Pinctrl-based I2C Bus Mux
10 - Wolfram Sang <wsa@kernel.org>
14 signals, and represents the pin multiplexing configuration using the pinctrl device tree
17 +-----+ +-----+
19 +------------------------+ +-----+ +-----+
21 | /----|------+--------+
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| D | qcom,i2c-qup.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/qcom,i2c-qup.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 - $ref: /schemas/i2c/i2c-controller.yaml#
20 - qcom,i2c-qup-v1.1.1 # for 8660, 8960 and 8064
21 - qcom,i2c-qup-v2.1.1 # for 8974 v1
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-bindings.txt | 4 such as pull-up/down, tri-state, drive-strength etc are designated as pin
15 need to reconfigure pins at run-time, for example to tri-state pins when the
17 states. The number and names of those states is defined by the client device's
20 The common pinctrl bindings defined in this file provide an infrastructure
21 for client device device tree nodes to map those state names to the pin
33 == Pinctrl client devices ==
38 assigned a name. When names are used, another property exists to map from
39 those names to the integer IDs.
43 IDs that must be provided, or whether to define the set of state names that
47 pinctrl-0: List of phandles, each pointing at a pin configuration
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| D | marvell,mvebu-pinctrl.txt | 1 * Marvell SoC pinctrl core driver for mpp
3 The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
7 Please refer to pinctrl-bindings.txt in this directory for details of the
8 common pinctrl bindings used by client devices, including the meaning of the
15 Required properties for pinctrl driver:
16 - compatible: "marvell,<soc>-pinctrl"
17 Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
20 - marvell,pins: string array of mpp pins or group of pins to be muxed.
21 - marvell,function: string representing a function to mux to for all
23 common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
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| D | amlogic,meson8-pinctrl-cbus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/amlogic,meson8-pinctrl-cbus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 - $ref: amlogic,meson-pinctrl-common.yaml#
18 - enum:
19 - amlogic,meson8-cbus-pinctrl
20 - amlogic,meson8b-cbus-pinctrl
21 - amlogic,meson-gxbb-periphs-pinctrl
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| D | amlogic,meson8-pinctrl-aobus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/amlogic,meson8-pinctrl-aobus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 - $ref: amlogic,meson-pinctrl-common.yaml#
18 - enum:
19 - amlogic,meson8-aobus-pinctrl
20 - amlogic,meson8b-aobus-pinctrl
21 - amlogic,meson-gxbb-aobus-pinctrl
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| D | amlogic,meson-pinctrl-a1.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/amlogic,meson-pinctrl-a1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 - $ref: amlogic,meson-pinctrl-common.yaml#
18 - amlogic,c3-periphs-pinctrl
19 - amlogic,t7-periphs-pinctrl
20 - amlogic,meson-a1-periphs-pinctrl
21 - amlogic,meson-s4-periphs-pinctrl
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| D | berlin,pinctrl.txt | 1 * Pin-controller driver for the Marvell Berlin SoCs
4 controller register sets. Pin controller nodes should be a sub-node of
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
21 "marvell,berlin2cd-system-pinctrl",
22 "marvell,berlin2q-soc-pinctrl",
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| D | axis,artpec6-pinctrl.txt | 1 Axis ARTPEC-6 Pin Controller
4 - compatible: "axis,artpec6-pinctrl".
5 - reg: Should contain the register physical address and length for the pin
8 A pinctrl node should contain at least one subnode representing the pinctrl
15 Required subnode-properties:
16 - function: Function to mux.
17 - groups: Name of the pin group to use for the function above.
49 Optional subnode-properties (see pinctrl-bindings.txt):
50 - drive-strength: 4, 6, 8, 9 mA. For SD and NAND pins, this is for 3.3V VCCQ3.
51 - bias-pull-up
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| D | sophgo,cv1800-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/sophgo,cv1800-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inochi Amaoto <inochiama@outlook.com>
15 - sophgo,cv1800b-pinctrl
16 - sophgo,cv1812h-pinctrl
17 - sophgo,sg2000-pinctrl
18 - sophgo,sg2002-pinctrl
22 - description: pinctrl for system domain
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| D | amlogic,meson-pinctrl-g12a-aobus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 - $ref: amlogic,meson-pinctrl-common.yaml#
18 - amlogic,meson-g12a-aobus-pinctrl
21 - compatible
24 "^bank@[0-9a-f]+$":
25 $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio
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| /Documentation/devicetree/bindings/rtc/ |
| D | rtc-omap.txt | 4 - compatible:
5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
12 - reg: Address range of rtc register set
13 - interrupts: rtc timer, alarm interrupts in order
16 - system-power-controller: whether the rtc is controlling the system power
18 - clocks: Any internal or external clocks feeding in to rtc
19 - clock-names: Corresponding names of the clocks
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| /Documentation/devicetree/bindings/media/ |
| D | stih407-c8sectpfe.txt | 14 - compatible : Should be "stih407-c8sectpfe"
16 - reg : Address and length of register sets for each device in
17 "reg-names"
19 - reg-names : The names of the register addresses corresponding to the
21 - c8sectpfe: c8sectpfe registers
22 - c8sectpfe-ram: c8sectpfe internal sram
24 - clocks : phandle list of c8sectpfe clocks
25 - clock-names : should be "c8sectpfe"
26 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
28 - pinctrl-names : a pinctrl state named tsin%d-serial or tsin%d-parallel (where %d is tsin-num)
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| D | atmel-isi.txt | 2 ----------------------------------
5 - compatible: must be "atmel,at91sam9g45-isi" or "microchip,sam9x60-isi".
6 - reg: physical base address and length of the registers set for the device.
7 - interrupts: should contain IRQ line for the ISI.
8 - clocks: list of clock specifiers, corresponding to entries in the clock-names
9 property; please refer to clock-bindings.txt.
10 - clock-names: required elements: "isi_clk".
11 - pinctrl-names, pinctrl-0: please refer to pinctrl-bindings.txt.
15 defined in Documentation/devicetree/bindings/media/video-interfaces.txt.
18 ------------------------
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| /Documentation/devicetree/bindings/serial/ |
| D | microchip,pic32-uart.txt | 4 - compatible: Should be "microchip,pic32mzda-uart"
5 - reg: Should contain registers location and length
6 - interrupts: Should contain interrupt
7 - clocks: Phandle to the clock.
8 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
9 - pinctrl-names: A pinctrl state names "default" must be defined.
10 - pinctrl-0: Phandle referencing pin configuration of the UART peripheral.
11 See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
14 - cts-gpios: CTS pin for UART
18 compatible = "microchip,pic32mzda-uart";
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| /Documentation/devicetree/bindings/net/ |
| D | microchip,enc28j60.txt | 9 - compatible: Should be "microchip,enc28j60"
10 - reg: Specify the SPI chip select the ENC28J60 is wired to
11 - interrupts: Specify the interrupt index within the interrupt controller (referred
12 to above in interrupt-parent) and interrupt type. The ENC28J60 natively
15 - pinctrl-names: List of assigned state names, see pinctrl binding documentation.
16 - pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line,
17 see also generic and your platform specific pinctrl binding
21 - spi-max-frequency: Maximum frequency of the SPI bus when accessing the ENC28J60.
31 compatible = "fsl,imx28-spi";
32 pinctrl-names = "default";
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| /Documentation/devicetree/bindings/pwm/ |
| D | pwm-st.txt | 2 --------------------------------------
5 - compatible : "st,pwm"
6 - #pwm-cells : Number of cells used to specify a PWM. First cell
7 specifies the per-chip index of the PWM to use and the
8 second cell is the period in nanoseconds - fixed to 2
10 - reg : Physical base address and length of the controller's
12 - pinctrl-names: Set to "default".
13 - pinctrl-0: List of phandles pointing to pin configuration nodes
15 For Pinctrl properties, please refer to [1].
16 - clock-names: Valid entries are "pwm" and/or "capture".
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| /Documentation/devicetree/bindings/net/bluetooth/ |
| D | mediatek,bluetooth.txt | 13 - compatible: Must be
14 "mediatek,mt7663u-bluetooth": for MT7663U device
15 "mediatek,mt7668u-bluetooth": for MT7668U device
16 - vcc-supply: Main voltage regulator
21 - pinctrl-names: Should be "default", "runtime"
22 - pinctrl-0: Should contain UART RXD low when the device is powered up to
24 - pinctrl-1: Should contain UART mode pin ctrl
30 - boot-gpios: GPIO same to the pin as UART RXD and used to keep LOW when
32 - pinctrl-names: Should be "default"
33 - pinctrl-0: Should contain UART mode pin ctrl
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| /Documentation/devicetree/bindings/mtd/ |
| D | st-fsm.txt | 1 * ST-Microelectronics SPI FSM Serial (NOR) Flash Controller
4 - compatible : Should be "st,spi-fsm"
5 - reg : Contains register's location and length.
6 - reg-names : Should contain the reg names "spi-fsm"
7 - interrupts : The interrupt number
8 - pinctrl-0 : Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt)
11 - st,syscfg : Phandle to boot-device system configuration registers
12 - st,boot-device-reg : Address of the aforementioned boot-device register(s)
13 - st,boot-device-spi : Expected boot-device value if booted via this device
17 compatible = "st,spi-fsm";
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