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/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-single.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Pin Controller with a Single Register for One or More Pins
10 - Tony Lindgren <tony@atomide.com>
13 Some pin controller devices use a single register for one or more pins. The
21 - enum:
22 - pinctrl-single
23 - pinconf-single
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Drenesas,rzn1-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - enum:
17 - renesas,r9a06g032-pinctrl # RZ/N1D
18 - renesas,r9a06g033-pinctrl # RZ/N1S
19 - const: renesas,rzn1-pinctrl # Generic RZ/N1
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Dpinctrl-bindings.txt4 such as pull-up/down, tri-state, drive-strength etc are designated as pin
14 single static pin configuration, e.g. set up during initialization. Others
15 need to reconfigure pins at run-time, for example to tri-state pins when the
20 The common pinctrl bindings defined in this file provide an infrastructure
27 in a single place, rather than splitting it across multiple client device
33 == Pinctrl client devices ==
47 pinctrl-0: List of phandles, each pointing at a pin configuration
52 from multiple nodes for a single pin controller, each
65 pinctrl-1: List of phandles, each pointing at a pin configuration
68 pinctrl-n: List of phandles, each pointing at a pin configuration
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Drenesas,rza2-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
19 Up to 8 different alternate function modes exist for each single pin.
23 const: renesas,r7s9210-pinctrl # RZ/A2M
28 gpio-controller: true
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Drenesas,rza1-ports.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
20 Up to 8 different alternate function modes exist for each single pin.
25 - const: renesas,r7s72100-ports # RZ/A1H
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Dpinmux-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
50 For cases like this, the pin controller driver may use pinctrl-pin-array helper
55 #pinctrl-cells = <2>;
58 pinctrl-pin-array = <
67 Above #pinctrl-cells specifies the number of value cells in addition to the
68 index of the registers. This is similar to the interrupts-extended binding with
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Dpinctrl-vt8500.txt1 VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller
7 - compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl",
8 "wm8750-pinctrl" or "wm,wm8850-pinctrl"
9 - reg: Should contain the physical address of the module's registers.
10 - interrupt-controller: Marks the device node as an interrupt controller.
11 - #interrupt-cells: Should be two.
12 - gpio-controller: Marks the device node as a GPIO controller.
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 bit 0 - active low
19 Please refer to pinctrl-bindings.txt in this directory for details of the
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Dcnxt,cx92755-pinctrl.txt11 - compatible: Must be "cnxt,cx92755-pinctrl"
12 - reg: Base address of the General Purpose Pin Mapping register block and the
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells: Must be <2>. The first cell is the pin number and the
16 second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h
21 pinctrl: pinctrl@f0000e20 {
22 compatible = "cnxt,cx92755-pinctrl";
24 gpio-controller;
25 #gpio-cells = <2>;
36 Each pin configuration node is a sub-node of the pin controller node and is a
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Drenesas,rzv2m-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzv2m-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
15 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
18 Up to 8 different alternate function modes exist for each single pin.
22 const: renesas,r9a09g011-pinctrl # RZ/V2M
27 gpio-controller: true
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Drenesas,rzg2l-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
19 Up to 8 different alternate function modes exist for each single pin.
24 - items:
25 - enum:
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Dbrcm,bcm2835-gpio.txt7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
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Dnuvoton,wpcm450-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
14 const: nuvoton,wpcm450-pinctrl
19 '#address-cells':
22 '#size-cells':
29 # 3. a pinconf node configures properties of a single pin
31 "^gpio@[0-7]$":
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Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
11 ST pinctrl driver controls PIO multiplexing block and also interacts with
14 GPIO bank can have one of the two possible types of interrupt-wirings.
16 First type is via irqmux, single interrupt is used by multiple gpio banks. This
18 a single pincontroller.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
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/Documentation/devicetree/bindings/arm/omap/
Dctrl.txt11 [1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
15 - compatible: Must be one of:
16 "ti,am3-scm"
17 "ti,am4-scm"
18 "ti,dm814-scrm"
19 "ti,dm816-scrm"
20 "ti,omap2-scm"
21 "ti,omap3-scm"
22 "ti,omap4-scm-core"
23 "ti,omap4-scm-padconf-core"
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/Documentation/devicetree/bindings/display/
Dtruly,nt35597.txt7 - compatible: should be "truly,nt35597-2K-display"
8 - vdda-supply: phandle of the regulator that provides the supply voltage
10 - vdispp-supply: phandle of the regulator that provides the supply voltage
12 - vdispn-supply: phandle of the regulator that provides the supply voltage
14 - reset-gpios: phandle of gpio for reset line
15 This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names
17 - mode-gpios: phandle of the gpio for choosing the mode of the display
18 for single DSI or Dual DSI
19 This should be low for dual DSI and high for single DSI mode
20 - ports: This device has two video ports driven by two DSIs. Their connections
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/Documentation/devicetree/bindings/sound/
Dmarvell,pxa2xx-ac97.txt6 - compatible: should be one of the following:
7 "marvell,pxa250-ac97"
8 "marvell,pxa270-ac97"
9 "marvell,pxa300-ac97"
10 - reg: device MMIO address space
11 - interrupts: single interrupt generated by AC97 IP
12 - clocks: input clock of the AC97 IP, refer to clock-bindings.txt
15 - pinctrl-names, pinctrl-0: refer to pinctrl-bindings.txt
16 - reset-gpios: gpio used for AC97 reset, refer to gpio.txt
20 compatible = "marvell,pxa250-ac97";
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Datmel,sama5d2-classd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/sound/atmel,sama5d2-classd.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Nicolas Ferre <nicolas.ferre@microchip.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - Claudiu Beznea <claudiu.beznea@microchip.com>
22 - items:
23 - const: atmel,sama5d2-classd
24 - items:
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/Documentation/devicetree/bindings/spi/
Dnuvoton,npcm-fiu.txt3 NPCM FIU supports single, dual and quad communication interface.
14 - compatible : "nuvoton,npcm750-fiu" for Poleg NPCM7XX BMC
15 "nuvoton,npcm845-fiu" for Arbel NPCM8XX BMC
16 - #address-cells : should be 1.
17 - #size-cells : should be 0.
18 - reg : the first contains the register location and length,
20 - reg-names: Should contain the reg names "control" and "memory"
21 - clocks : phandle of FIU reference clock.
24 - pinctrl-names : a pinctrl state named "default" must be defined.
25 - pinctrl-0 : phandle referencing pin configuration of the device.
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/Documentation/devicetree/bindings/media/
Datmel-isi.txt2 ----------------------------------
5 - compatible: must be "atmel,at91sam9g45-isi" or "microchip,sam9x60-isi".
6 - reg: physical base address and length of the registers set for the device.
7 - interrupts: should contain IRQ line for the ISI.
8 - clocks: list of clock specifiers, corresponding to entries in the clock-names
9 property; please refer to clock-bindings.txt.
10 - clock-names: required elements: "isi_clk".
11 - pinctrl-names, pinctrl-0: please refer to pinctrl-bindings.txt.
13 ISI supports a single port node with parallel bus. It shall contain one
15 defined in Documentation/devicetree/bindings/media/video-interfaces.txt.
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Dti-am437x-vpfe.txt2 --------------------------------------
6 processing capability to connect RAW image-sensor modules and video decoders
10 - compatible: must be "ti,am437x-vpfe"
11 - reg: physical base address and length of the registers set for the device;
12 - interrupts: should contain IRQ line for the VPFE;
13 - ti,am437x-vpfe-interface: can be one of the following,
14 0 - Raw Bayer Interface.
15 1 - 8 Bit BT656 Interface.
16 2 - 10 Bit BT656 Interface.
17 3 - YCbCr 8 Bit Interface.
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/Documentation/devicetree/bindings/display/tilcdc/
Dtilcdc.txt1 Device-Tree bindings for tilcdc DRM driver
4 - compatible: value should be one of the following:
5 - "ti,am33xx-tilcdc" for AM335x based boards
6 - "ti,da850-tilcdc" for DA850/AM18x/OMAP-L138 based boards
7 - interrupts: the interrupt number
8 - reg: base address and size of the LCDC device
11 - ti,hwmods: Name of the hwmod associated to the LCDC
14 - max-bandwidth: The maximum pixels per second that the memory
16 - max-width: The maximum horizontal pixel width supported by
18 - max-pixelclock: The maximum pixel clock that can be supported
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/Documentation/devicetree/bindings/display/bridge/
Dite,it66121.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Phong LE <ple@baylibre.com>
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The IT66121 is a high-performance and low-power single channel HDMI
21 - ite,it66121
22 - ite,it6610
27 reset-gpios:
31 vrf12-supply:
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/Documentation/devicetree/bindings/soc/mobileye/
Dmobileye,eyeq5-olb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq5-olb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grégory Clement <gregory.clement@bootlin.com>
11 - Théo Lebrun <theo.lebrun@bootlin.com>
12 - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
16 resets, pinctrl are being handled from here. EyeQ5 and EyeQ6L host a single
22 - enum:
23 - mobileye,eyeq5-olb
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/Documentation/devicetree/bindings/soc/qcom/
Dqcom,geni-se.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
15 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
23 - qcom,geni-se-qup
24 - qcom,geni-se-i2c-master-hub
30 clock-names:
38 "#address-cells":
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/Documentation/devicetree/bindings/mfd/
Dqcom,pm8008.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guru Das Srinagesh <quic_gurus@quicinc.com>
15 functions into a single IC.
27 reset-gpios:
30 vdd-l1-l2-supply: true
31 vdd-l3-l4-supply: true
32 vdd-l5-supply: true
33 vdd-l6-supply: true
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