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/Documentation/devicetree/bindings/pinctrl/
Dloongson,ls2k-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/loongson,ls2k-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-2 SoC Pinctrl Controller
10 - zhanghongchen <zhanghongchen@loongson.cn>
11 - Yinbo Zhu <zhuyinbo@loongson.cn>
14 - $ref: pinctrl.yaml#
18 const: loongson,ls2k-pinctrl
24 '-pins$':
[all …]
Dnvidia,tegra234-pinmux-aon.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-aon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra234 AON Pinmux Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-pinmux-aon
21 "^pinmux(-[a-z0-9-]+)?$":
26 $ref: nvidia,tegra234-pinmux-common.yaml
[all …]
Dbrcm,ns-pinmux.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,ns-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafał Miłecki <rafal@milecki.pl>
23 - brcm,bcm4708-pinmux
24 - brcm,bcm4709-pinmux
25 - brcm,bcm53012-pinmux
30 reg-names:
34 '-pins$':
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Dintel,lgm-io.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain SoC pinmux & GPIO controller
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
13 Pinmux & GPIO controller controls pin multiplexing & configuration including
18 const: intel,lgm-io
25 '-pins$':
30 $ref: pinmux-node.yaml#
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Dnvidia,tegra124-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra124-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 Pinmux Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 Tegra30 pinctrl binding, as described in nvidia,tegra20-pinmux.yaml and
15 nvidia,tegra30-pinmux.yaml. In fact, this document assumes that binding as a
21 - const: nvidia,tegra124-pinmux
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Dnvidia,tegra210-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra210-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 Pinmux Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra210-pinmux
19 - description: APB_MISC_GP_*_PADCTRL register (pad control)
20 - description: PINMUX_AUX_* registers (pinmux)
[all …]
Dpinmux-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
50 For cases like this, the pin controller driver may use pinctrl-pin-array helper
55 #pinctrl-cells = <2>;
58 pinctrl-pin-array = <
67 Above #pinctrl-cells specifies the number of value cells in addition to the
68 index of the registers. This is similar to the interrupts-extended binding with
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Dnvidia,tegra194-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra194-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 Pinmux Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra194-pinmux
17 - nvidia,tegra194-pinmux-aon
21 - description: pinmux registers
[all …]
Dnxp,s32g2-siul2-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul2-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ghennadi Procopciuc <Ghennadi.Procopciuc@oss.nxp.com>
12 - Chester Lin <chester62515@gmail.com>
15 S32G2 pinmux is implemented in SIUL2 (System Integration Unit Lite2),
21 IMCR registers need to be revealed for kernel to configure pinmux.
24 MSCR102-MSCR111, MSCR123-MSCR143, IMCR84-IMCR118 and IMCR398-IMCR429.
29 - nxp,s32g2-siul2-pinctrl
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Drenesas,rzn1-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - enum:
17 - renesas,r9a06g032-pinctrl # RZ/N1D
18 - renesas,r9a06g033-pinctrl # RZ/N1S
19 - const: renesas,rzn1-pinctrl # Generic RZ/N1
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Dnvidia,tegra234-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra234 Pinmux Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-pinmux
21 "^pinmux(-[a-z0-9-]+)?$":
26 $ref: nvidia,tegra234-pinmux-common.yaml
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Dmediatek,mt8195-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
32 gpio-line-names: true
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Dmediatek,mt65xx-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl
22 - mediatek,mt8127-pinctrl
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Dsophgo,cv1800-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/sophgo,cv1800-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inochi Amaoto <inochiama@outlook.com>
15 - sophgo,cv1800b-pinctrl
16 - sophgo,cv1812h-pinctrl
17 - sophgo,sg2000-pinctrl
18 - sophgo,sg2002-pinctrl
22 - description: pinctrl for system domain
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Datmel,at91-pio4-pinctrl.txt7 - compatible:
8 "atmel,sama5d2-pinctrl"
9 "microchip,sama7g5-pinctrl"
10 - reg: base address and length of the PIO controller.
11 - interrupts: interrupt outputs from the controller, one for each bank.
12 - interrupt-controller: mark the device node as an interrupt controller.
13 - #interrupt-cells: should be two.
14 - gpio-controller: mark the device node as a gpio controller.
15 - #gpio-cells: should be two.
17 Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
[all …]
Dnvidia,tegra114-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra114-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra114 pinmux Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra114-pinmux
19 - description: pad control registers
20 - description: mux registers
[all …]
Dmediatek,mt8186-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8186-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
31 gpio-line-names: true
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Dbrcm,nsp-pinmux.txt7 - compatible:
8 Must be "brcm,nsp-pinmux"
10 - reg:
15 - function:
18 - groups:
22 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
26 pinmux: pinmux@1803f1c0 {
27 compatible = "brcm,nsp-pinmux";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pwm>, <&gpio_b>, <&nand_sel>;
Drenesas,rza1-ports.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
25 - const: renesas,r7s72100-ports # RZ/A1H
26 - items:
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Dnvidia,tegra20-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra20-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 Pinmux Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra20-pinmux
19 - description: tri-state registers
20 - description: mux register
[all …]
Dpinctrl_spear.txt1 ST Microelectronics, SPEAr pinmux controller
4 - compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux"
7 : "st,spear1310-pinmux"
8 : "st,spear1340-pinmux"
9 - reg : Address range of the pinctrl registers
10 - st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
11 - Its values for SPEAr300:
12 - NAND_MODE : <0>
[all …]
Drenesas,rza2-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
23 const: renesas,r7s9210-pinctrl # RZ/A2M
28 gpio-controller: true
30 '#gpio-cells':
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Dbrcm,cygnus-pinmux.txt8 - compatible:
9 Must be "brcm,cygnus-pinmux"
11 - reg:
17 - function:
20 - groups:
24 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
28 pinmux: pinmux@0301d0c8 {
29 compatible = "brcm,cygnus-pinmux";
32 pinctrl-names = "default";
33 pinctrl-0 = <&i2s0_default>;
Dmediatek,mt6795-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 - Sean Wang <sean.wang@kernel.org>
18 const: mediatek,mt6795-pinctrl
20 gpio-controller: true
22 '#gpio-cells':
29 gpio-ranges:
[all …]
Dcanaan,k210-fpioa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpioa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <dlemoal@kernel.org>
16 a per-pin basis.
20 const: canaan,k210-fpioa
29 - description: Controller reference clock source
30 - description: APB interface clock source
32 clock-names:
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