Searched full:pipe (Results 1 – 25 of 129) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ |
| D | qcom,gcc-sc8280xp.yaml | 32 - description: Primary USB SuperSpeed pipe clock
36 - description: USB4 PHY PCIe pipe clock
37 - description: USB4 PHY router max pipe clock
40 - description: Secondary USB SuperSpeed pipe clock
44 - description: Second USB4 PHY PCIe pipe clock
45 - description: Second USB4 PHY router max pipe clock
48 - description: Multiport USB first SuperSpeed pipe clock
49 - description: Multiport USB second SuperSpeed pipe clock
50 - description: PCIe 2a pipe clock
51 - description: PCIe 2b pipe clock
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| D | qcom,ipq9574-gcc.yaml | 30 - description: PCIE30 PHY0 pipe clock source
31 - description: PCIE30 PHY1 pipe clock source
32 - description: PCIE30 PHY2 pipe clock source
33 - description: PCIE30 PHY3 pipe clock source
34 - description: USB3 PHY pipe clock source
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| D | qcom,x1e80100-gcc.yaml | 26 - description: PCIe 3 pipe clock
27 - description: PCIe 4 pipe clock
28 - description: PCIe 5 pipe clock
29 - description: PCIe 6a pipe clock
30 - description: PCIe 6b pipe clock
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| D | qcom,gcc-msm8996.yaml | 29 - description: PCIe 0 PIPE clock (optional)
30 - description: PCIe 1 PIPE clock (optional)
31 - description: PCIe 2 PIPE clock (optional)
32 - description: USB3 PIPE clock (optional)
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| D | qcom,sdx75-gcc.yaml | 36 - description: PCIE_1 Pipe clock source
37 - description: PCIE_2 Pipe clock source
38 - description: PCIE Pipe clock source
39 - description: USB3 phy wrapper pipe clock source
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| D | qcom,sa8775p-gcc.yaml | 32 - description: Primary USB3 PHY wrapper pipe clock
33 - description: Secondary USB3 PHY wrapper pipe clock
34 - description: PCIe 0 pipe clock
35 - description: PCIe 1 pipe clock
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| D | qcom,ipq5332-gcc.yaml | 29 - description: PCIE 2lane PHY pipe clock source
30 - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
31 - description: USB PCIE wrapper pipe clock source
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| D | qcom,gcc-sm8350.yaml | 26 - description: PCIE 0 Pipe clock source (Optional clock)
27 - description: PCIE 1 Pipe clock source (Optional clock)
34 - description: USB3 phy wrapper pipe clock source (Optional clock)
35 - description: USB3 phy sec pipe clock source (Optional clock)
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| D | qcom,ipq5018-gcc.yaml | 28 - description: PCIE20 PHY0 pipe clock source
29 - description: PCIE20 PHY1 pipe clock source
30 - description: USB3 PHY pipe clock source
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| D | qcom,sm8550-gcc.yaml | 26 - description: PCIE 0 Pipe clock source
27 - description: PCIE 1 Pipe clock source
32 - description: USB3 Phy wrapper pipe clock source
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| D | qcom,sm8650-gcc.yaml | 27 - description: PCIE 0 Pipe clock source
28 - description: PCIE 1 Pipe clock source
33 - description: USB3 Phy wrapper pipe clock source
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-rockchip-naneng-combphy.yaml | 25 - description: pipe clock
31 - const: pipe
64 rockchip,pipe-grf:
69 rockchip,pipe-phy-grf:
72 Some additional pipe settings are accessed through GRF regs.
83 - rockchip,pipe-grf
84 - rockchip,pipe-phy-grf
120 compatible = "rockchip,rk3568-pipe-grf", "syscon";
125 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
135 clock-names = "ref", "apb", "pipe";
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| D | phy-rockchip-typec.txt | 16 "uphy", "uphy-pipe", "uphy-tcphy"
35 - rockchip,pipe-status
51 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
75 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
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| D | qcom,pcie2-phy.yaml | 28 - description: a clock-specifier pair for the "pipe" clock
51 - const: pipe
77 reset-names = "phy", "pipe";
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| /Documentation/devicetree/bindings/goldfish/ |
| D | pipe.txt | 1 Android Goldfish QEMU Pipe
3 Andorid pipe virtual device generated by android emulator.
7 - compatible : should contain "google,android-pipe" to match emulator
14 compatible = "google,android-pipe";
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| /Documentation/gpu/amdgpu/display/ |
| D | mpo-overview.rst | 50 For this hardware example, we have 4 pipes (if you don't know what AMD pipe
52 "AMD Hardware Pipeline"). Typically most AMD devices operate in a pipe-split
58 At least 1 pipe must be used per plane (primary and overlay), so for this
161 - ``kms_plane@plane-panning-bottom-right-pipe-*-planes``
162 - ``kms_plane@plane-panning-bottom-right-suspend-pipe-*-``
163 - ``kms_plane@plane-panning-top-left-pipe-*-``
164 - ``kms_plane@plane-position-covered-pipe-*-``
165 - ``kms_plane@plane-position-hole-dpms-pipe-*-``
166 - ``kms_plane@plane-position-hole-pipe-*-``
167 - ``kms_plane_multiple@atomic-pipe-*-tiling-``
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| D | dc-debug.rst | 33 * Pipe split can be observed if there are two bars with a difference in height
38 feature one or two green bars at the bottom of the video depending on pipe
48 Pipe Split Debug
57 In this case, if you have a pipe split, you will see one small red bar at the
59 covering the second pipe. In other words, you will see a bit high bar in the
60 second pipe.
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| D | dcn-overview.rst | 19 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
23 * **Multiple Pipe/Plane Combined (MPC)**: This component performs blending of
29 * **Output Pipe Timing Combiner (OPTC)**: It generates time output to combine
36 the display pipe back to memory as video frames.
54 the SDP as the element from our Data Fabric that feeds the display pipe.
133 pipeline** or **pipeline** or just **pipe** as an abstraction to indicate a
137 In actuality, we can't connect an arbitrary block from one pipe to a block from
138 another pipe; they are routed linearly, except for DSC, which can be
162 we can split this single pipe differently, as described in the below diagram:
182 that the pipe configuration can vary a lot according to the display
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| /Documentation/devicetree/bindings/media/ |
| D | microchip,csi2dc.yaml | 25 CSI2DC provides two pipes, one video pipe and one data pipe. Video pipe
26 is connected at the output to a sensor controller and the data pipe is
33 This is called video pipe.
38 called data pipe.
39 For data pipe to be available, a dma controller and a dma channel must be
142 # Example for connecting to a parallel sensor controller block (video pipe)
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| D | mediatek,mdp3-rdma.yaml | 77 - description: used for 1st data pipe from RDMA
78 - description: used for 2nd data pipe from RDMA
79 - description: used for 3rd data pipe from RDMA
80 - description: used for 4th data pipe from RDMA
81 - description: used for the data pipe from SPLIT
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| /Documentation/driver-api/ |
| D | xillybus.rst | 21 -- Pipe attributes
79 elementary data transport between an FPGA and the host, providing pipe-like
92 just like any pipe file. On the FPGA side, hardware FIFOs are used to stream
118 and use plain write() or read() calls, just like with a regular pipe. In
145 asynchronous. For a synchronous pipe, write() returns successfully only after
151 When a pipe is configured asynchronous, write() returns if there was enough
172 A synchronous pipe can be configured to have the stream's position exposed
173 to the user logic at the FPGA. Such a pipe is also seekable on the host API.
196 Pipe attributes
199 Each pipe has a number of attributes which are set when the FPGA component
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| /Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie.yaml | 307 - const: pipe # PIPE reset
313 - const: pipe_sticky # PIPE sticky reset
331 - const: pipe # Pipe Clock driving internal logic
362 - const: pipe # PIPE reset
394 - const: pipe # PIPE reset
428 - const: pipe_sticky # PIPE sticky reset
447 - const: pipe # PIPE clock
461 - const: pipe # PIPE clock
488 - const: pipe # PIPE clock
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| D | rockchip-dw-pcie-common.yaml | 27 - description: PIPE clock
38 - const: pipe
106 - const: pipe
109 - const: pipe
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| /Documentation/devicetree/bindings/usb/ |
| D | hisilicon,histb-xhci.txt | 14 "pipe": for pipe clock
40 clock-names = "bus", "utmi", "pipe", "suspend";
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| /Documentation/filesystems/ |
| D | splice.rst | 16 Pipe interfaces are all for in-kernel (builtin image) use. They are not
22 .. kernel-doc:: fs/pipe.c
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