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/Documentation/devicetree/bindings/display/bridge/
Dfsl,imx8qxp-pixel-link.yaml4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
7 title: Freescale i.MX8qm/qxp Display Pixel Link
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
14 asynchronous linkage between pixel sources(display controller or
15 camera module) and pixel consumers(imaging or displays).
16 It consists of two distinct functions, a pixel transfer function and a
17 control interface. Multiple pixel channels can exist per one control channel.
18 This binding documentation is only for pixel links whose pixel sources are
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
27 - fsl,imx8qm-dc-pixel-link
[all …]
Dfsl,imx8qxp-pixel-combiner.yaml4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#
7 title: Freescale i.MX8qm/qxp Pixel Combiner
13 The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
15 of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
16 either one screen, two screens, or virtual screens. The pixel combiner is
17 also responsible for generating some of the control signals for the pixel link
23 - fsl,imx8qm-pixel-combiner
24 - fsl,imx8qxp-pixel-combiner
47 description: Represents a display stream of pixel combiner.
92 pixel-combiner@56020000 {
[all …]
Dfsl,imx8qxp-pxl2dpi.yaml7 title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
13 The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
14 interfaces the pixel link 36-bit data output and the DSI controller’s
16 used in LVDS mode, to remap the pixel color codings between those modules.
46 description: The PXL2DPI input port node from pixel link.
/Documentation/devicetree/bindings/arm/
Dgoogle.yaml13 ARM platforms using SoCs designed by Google branded "Tensor" used in Pixel
16 Currently upstream this is devices using "gs101" SoC which is found in Pixel
17 6, Pixel 6 Pro and Pixel 6a.
26 - Marketing name ("Pixel 6")
37 - description: Google Pixel 6 / Oriole
/Documentation/userspace-api/media/v4l/
Dfourcc.rst3 Guidelines for Video4Linux pixel format 4CCs
8 the pixel format, compression and colour space. The interpretation of the
23 2nd character: pixel order
30 3rd character: uncompressed bits-per-pixel 0--9, A--
32 4th character: compressed bits-per-pixel 0--9, A--
Dvidioc-enum-framesizes.rst30 that contains an index and pixel format and receives a frame width
37 and height in pixels) that the device supports for the given pixel
40 The supported pixel formats can be obtained by using the
99 - Width of the frame [pixel].
102 - Height of the frame [pixel].
114 - Minimum frame width [pixel].
117 - Maximum frame width [pixel].
120 - Frame width step size [pixel].
123 - Minimum frame height [pixel].
126 - Maximum frame height [pixel].
[all …]
Dext-ctrls-image-process.rst28 .. _v4l2-cid-pixel-rate:
31 Pixel sampling rate in the device's pixel array. This control is
35 rate. The frame rate can be calculated from the pixel rate, analogue crop
36 rectangle as well as horizontal and vertical blanking. The pixel rate
Dpixfmt-intro.rst29 leftmost pixel of the topmost row. Following that is the pixel
31 pixels. Following the rightmost pixel of the row there may be zero or
32 more bytes of padding to guarantee that each row of pixel data has a
34 leftmost pixel of the second row from the top, and so on. The last row
Dpixfmt-y12i.rst15 This is a grey-scale image with a depth of 12 bits per pixel, but with
16 pixels from 2 sources interleaved and bit-packed. Each pixel is stored
28 interleaved pixel.
/Documentation/gpu/amdgpu/display/
Ddisplay-manager.rst90 Pixel blend mode is a DRM plane composition property of :c:type:`drm_plane` used to
99 pixel color values and, therefore, the resulted pixel color. For
102 - *fg.rgb*: Each of the RGB component values from the foreground's pixel.
103 - *fg.alpha*: Alpha component value from the foreground's pixel.
112 the alpha channel value of each pixel in a plane is ignored and only the plane
113 alpha affects the resulted pixel color values.
117 * **None**: Blend formula that ignores the pixel alpha.
119 * **Pre-multiplied**: Blend formula that assumes the pixel color values in a
122 * **Coverage**: Blend formula that assumes the pixel color values were not
125 and pre-multiplied is the default pixel blend mode, that means, when no blend
[all …]
Ddc-glossary.rst31 Bits Per Pixel
34 * PCLK: Pixel Clock
41 * PPLL: Pixel PLL
50 raw stream of pixels, clocked at pixel clock
95 Display Stream Compression (Reduce the amount of bits to represent pixel
96 count while at the same pixel clock)
Ddcn-overview.rst19 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
20 processing such as color space conversion, linearization of pixel data, tone
24 multiple planes, using global or per-pixel alpha.
26 * **Output Pixel Processing (OPP)**: Process and format pixels to be sent to
66 1. Pixel data interface (red): Represents the pixel data flow;
102 is to change, blend and compose pixel data, while BE's job is to frame a
103 generic pixel stream to a specific display's pixel stream.
108 Initially, data is passed in from VRAM through Data Fabric (DF) in native pixel
110 different pixel formats and outputs them to DPP in uniform streams through 4
194 in order to support outputs that need a very high pixel clock, or for
/Documentation/devicetree/bindings/media/
Dcdns,csi2rx.yaml14 lanes in input, and 4 different pixel streams in output.
31 - description: pixel Clock for Stream interface 0
32 - description: pixel Clock for Stream interface 1
33 - description: pixel Clock for Stream interface 2
34 - description: pixel Clock for Stream interface 3
49 - description: pixel reset for Stream interface 0
50 - description: pixel reset for Stream interface 1
51 - description: pixel reset for Stream interface 2
52 - description: pixel reset for Stream interface 3
/Documentation/devicetree/bindings/display/armada/
Dmarvell,dove-lcd.txt13 "axiclk" - axi bus clock for pixel clock
14 "plldivider" - pll divider clock for pixel clock
15 "ext_ref_clk0" - external clock 0 for pixel clock
16 "ext_ref_clk1" - external clock 1 for pixel clock
/Documentation/driver-api/media/
Dtx-rx.rst5 Pixel data transmitter and receiver drivers
8 V4L2 supports various devices that transmit and receive pixel data. Examples of
41 Media bus pixel code
62 Pixel rate
65 The pixel rate on the bus is calculated as follows::
71 .. list-table:: variables in pixel rate calculation
90 The pixel rate calculated this way is **not** the same thing as the
91 pixel rate on the camera sensor's pixel array which is indicated by the
92 :ref:`V4L2_CID_PIXEL_RATE <v4l2-cid-pixel-rate>` control.
/Documentation/userspace-api/
Ddma-buf-alloc-exchange.rst5 Exchanging pixel buffers
9 support for sharing pixel-buffer allocations between processes, devices, and
26 in one or more memory buffers. Has width and height in pixels, pixel
41 A piece of memory for storing (parts of) pixel data. Has stride and size
49 pixel:
54 pixel data:
56 of a pixel or an image. The data for one pixel may be spread over several
68 pixel format:
69 A description of how pixel data represents the pixel's color and alpha
73 A description of how pixel data is laid out in memory buffers.
[all …]
/Documentation/devicetree/bindings/bus/
Dfsl,imx8qxp-pixel-link-msi-bus.yaml4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
13 i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
29 pixel link MSI bus controller and does not allow SCFW user to control it.
43 - fsl,imx8qxp-display-pixel-link-msi-bus
44 - fsl,imx8qm-display-pixel-link-msi-bus
52 - fsl,imx8qxp-display-pixel-link-msi-bus
53 - fsl,imx8qm-display-pixel-link-msi-bus
94 compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus";
[all …]
/Documentation/devicetree/bindings/media/i2c/
Daptina,mt9p031.yaml13 The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor
60 pixel-clock-frequency:
63 description: Target pixel clock frequency
70 - pixel-clock-frequency
103 pixel-clock-frequency = <96000000>;
/Documentation/devicetree/bindings/display/msm/
Ddsi-controller-main.yaml68 - pixel:: Display pixel clock.
109 Parents of "byte" and "pixel" for the given platform.
117 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
241 - const: pixel
260 - const: pixel
280 - const: pixel
300 - const: pixel
321 - const: pixel
340 - const: pixel
367 - const: pixel
[all …]
/Documentation/userspace-api/media/drivers/
Dcamera-sensor.rst25 of cropping and scaling operations from the device's pixel array's size.
58 (analogue crop height + vertical blanking) / pixel rate
62 crop, use the full source image size, i.e. pixel array size.
66 is pixels and the unit of the ``V4L2_CID_VBLANK`` is lines. The pixel rate in
67 the sensor's **pixel array** is specified by ``V4L2_CID_PIXEL_RATE`` in the same
74 The first entity in the linear pipeline is the pixel array. The pixel array may
Dccs.rst12 camera sensors. It exposes three sub-devices representing the pixel array,
20 Pixel Array sub-device
23 The pixel array sub-device represents the camera sensor's pixel matrix, as well
26 entity. The size of the pixel matrix can be obtained by getting the
59 analogue data is never read from the pixel matrix that are outside the
/Documentation/fb/
Dpxafb.rst33 Pixel clock in picoseconds
63 4 or 8 pixel monochrome single panel data
72 Double pixel clock. 1=>true, 0=>false
80 pixel clock polarity
112 bpp = 16 -- for YUV422 planar (1 pixel = 1 Y + 1/2 Cb + 1/2 Cr)
114 bpp = 12 -- for YUV420 planar (1 pixel = 1 Y + 1/4 Cb + 1/4 Cr)
123 with minimum bits per pixel, e.g. for YUV420, Cr component
124 for one pixel is actually 2-bits, it means the line length
/Documentation/userspace-api/media/dvb/
Dlegacy_dvb_osd.rst130 - | Sets all pixel to color 0.
139 - | Sets all pixel to color <color>.
153 | opacity=0: pixel opacity 0% (only video pixel shows)
154 | opacity=1..254: pixel opacity as specified in header
155 | opacity=255: pixel opacity 100% (only OSD pixel shows)
170 255->pixel
178 - | Sets transparency of mixed pixel (0..15).
187 - | Sets pixel <x>,<y> to color number <color>.
196 - | Returns color number of pixel <x>,<y>, or -1.
206 | Returns 0 on success, -1 on clipping all pixel (no pixel
[all …]
/Documentation/devicetree/bindings/display/
Dbrcm,bcm2835-dpi.yaml22 - description: The pixel clock that feeds the pixelvalve
27 - const: pixel
52 clock-names = "core", "pixel";
/Documentation/devicetree/bindings/clock/
Dfsl,plldig.yaml7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock
15 which generate and offers pixel clocks to Display.
49 # Display PIXEL Clock node:

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