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/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
26 with priority below this threshold will not cause the PLIC to raise its
29 The PLIC supports both edge-triggered and level-triggered interrupts. For
30 edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31 seen while an interrupt handler is active; the PLIC may either queue them or
36 RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
38 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
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Driscv,cpu-intc.yaml23 (PLIC).
28 tree entry, though external interrupt controllers (like the PLIC, for
30 This means a PLIC interrupt property will typically list the HLICs for all
Dstarfive,jh8100-intc.yaml12 interrupt signal to RISC-V PLIC.
/Documentation/devicetree/bindings/net/can/
Dmicrochip,mpfs-can.yaml45 interrupt-parent = <&plic>;
/Documentation/devicetree/bindings/usb/
Dmicrochip,mpfs-musb.yaml60 interrupt-parent = <&plic>;
/Documentation/devicetree/bindings/i2c/
Dmicrochip,corei2c.yaml52 interrupt-parent = <&plic>;
/Documentation/devicetree/bindings/spi/
Dmicrochip,mpfs-spi.yaml83 interrupt-parent = <&plic>;
Dspi-sifive.yaml78 interrupt-parent = <&plic>;
/Documentation/devicetree/bindings/gpio/
Dsifive,gpio.yaml82 interrupt-parent = <&plic>;
Dmicrochip,mpfs-gpio.yaml82 interrupt-parent = <&plic>;
/Documentation/devicetree/bindings/pwm/
Dpwm-sifive.yaml69 interrupt-parent = <&plic>;
/Documentation/devicetree/bindings/pci/
Dstarfive,jh7110-pcie.yaml92 interrupt-parent = <&plic>;