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/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
20 This property is only valid when compatible = "ti,da850-pll0".
42 This child node is only valid when compatible = "ti,da850-pll0".
56 pll0: clock-controller@11000 {
57 compatible = "ti,da850-pll0";
/Documentation/devicetree/bindings/clock/
Dfsl,qoriq-clock.yaml166 pll0: pll0@800 {
171 clock-output-names = "pll0", "pll0-div2";
186 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
187 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
195 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
196 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dmicrochip,mpfs-ccc.yaml24 - description: PLL0's control registers
35 - description: PLL0's refclk0
36 - description: PLL0's refclk1
Dstarfive,jh7110-syscrg.yaml30 - description: PLL0
44 - description: PLL0
Dsilabs,si5351.yaml216 /* Use XTAL input as source of PLL0 and PLL1 */
225 * - PLL0 as clock source of multisynth 0
227 * - Multisynth 0 can change PLL0
Drenesas,cpg-clocks.yaml78 - const: pll0
204 - const: pll0
Dimx28-clock.yaml20 pll0 1
Drenesas,cpg-div6-clock.yaml60 clock-output-names = "main", "pll0", "pll1", "pll2",
/Documentation/devicetree/bindings/clock/st/
Dst,clkgen-pll.txt12 "st,clkgen-pll0"
13 "st,clkgen-pll0-a0"
14 "st,clkgen-pll0-c0"
Dst,clkgen.txt51 compatible = "st,clkgen-pll0";
Dst,flexgen.txt21 | | |PLL0 | | | | |Dividers| |Dividers| | |
/Documentation/devicetree/bindings/display/
Dintel,keembay-display.yaml28 - description: pll0 clock
/Documentation/devicetree/bindings/phy/
Dphy-cadence-torrent.yaml39 PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
42 Same refclk is used for both PLL0 and PLL1 if no separate pll1_refclk is used.
Dti,phy-j721e-wiz.yaml216 pll0-refclk {