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/Documentation/devicetree/bindings/pinctrl/
Dqcom,pmic-mpp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,pmic-mpp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PMIC Multi-Purpose Pin (MPP) block
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 This binding describes the MPP block(s) found in the 8xxx series of
14 PMIC's from Qualcomm.
19 - items:
20 - enum:
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Dmarvell,dove-pinctrl.txt1 * Marvell Dove SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
11 Available mpp pins/groups and functions:
12 Note: brackets (x) are not part of the mpp name for marvell,function and given
23 uart1(cts), lcd-spi(cs1), pmu*
31 mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
39 mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
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/Documentation/devicetree/bindings/mfd/
Dqcom-pm8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/qcom-pm8xxx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PM8xxx PMIC multi-function devices
10 - Satya Priya <quic_c_skakit@quicinc.com>
19 - enum:
20 - qcom,pm8058
21 - qcom,pm8821
22 - qcom,pm8901
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Dqcom,spmi-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SPMI PMICs multi-function device
13 16-bit SPMI peripheral address space into 256 smaller fixed-size regions, 256 bytes
14 each. A function can consume one or more of these fixed-size register regions.
24 - Stephen Boyd <sboyd@kernel.org>
29 - pattern: '^pmic@.*$'
30 - pattern: '^pm(a|s)?[0-9]*@.*$'
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/Documentation/devicetree/bindings/rtc/
Disil,isl12057.txt8 ("wakeup-source") to handle the specific use-case found
9 on at least three in-tree users of the chip (NETGEAR ReadyNAS 102, 104
10 and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip
12 to the SoC but to a PMIC. It allows the device to be powered up when
20 - "compatible": must be "isil,isl12057"
21 - "reg": I2C bus address of the device
25 - "wakeup-source": mark the chip as a wakeup source, independently of
38 that the pinctrl-related properties below are given for completeness and
40 SoC, and the main function of the MPP used as IRQ line, i.e.
41 "interrupt-parent" and "interrupts" are usually sufficient):
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