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/Documentation/devicetree/bindings/mmc/
Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
47 non-removable:
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/Documentation/driver-api/
Dpwm.rst15 ----------------
24 PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight", NULL,
36 ----------
65 If supported by the driver, the signal can be optimized, for example to improve
82 PWM arguments are usually platform-specific and allows the PWM user to only
84 period). struct pwm_args contains 2 fields (period and polarity) and should
93 -----------------------------------
102 The number of PWM channels this chip supports (read-only).
105 Exports a PWM channel for use with sysfs (write-only).
108 Unexports a PWM channel from sysfs (write-only).
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/Documentation/devicetree/bindings/net/pse-pd/
Dti,tps23881.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/pse-pd/ti,tps23881.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kory Maincent <kory.maincent@bootlin.com>
13 - $ref: pse-controller.yaml#
18 - ti,tps23881
23 '#pse-cells':
26 reset-gpios:
38 "#address-cells":
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Dmicrochip,pd692x0.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/pse-pd/microchip,pd692x0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kory Maincent <kory.maincent@bootlin.com>
13 - $ref: pse-controller.yaml#
18 - microchip,pd69200
19 - microchip,pd69210
20 - microchip,pd69220
40 "#address-cells":
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Dpse-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/pse-pd/pse-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 power over twisted pair/ethernet cable. The ethernet-pse nodes should be
12 used to describe PSE controller and referenced by the ethernet-phy node.
15 - Oleksij Rempel <o.rempel@pengutronix.de>
16 - Kory Maincent <kory.maincent@bootlin.com>
20 pattern: "^ethernet-pse(@.*|-([0-9]|[1-9][0-9]+))?$"
22 "#pse-cells":
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/Documentation/devicetree/bindings/media/i2c/
Dst,st-vgxy61.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/i2c/st,st-vgxy61.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Benjamin Mugnier <benjamin.mugnier@foss.st.com>
12 - Sylvain Petinot <sylvain.petinot@foss.st.com>
14 description: |-
15 STMicroelectronics VGxy61 family has a CSI-2 output port. CSI-2 output is a
17 Supported formats are RAW8, RAW10, RAW12, RAW14 and RAW16.
18 Following part number are supported
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/Documentation/devicetree/bindings/display/panel/
Dpanel-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
24 width-mm:
29 height-mm:
43 non-descriptive information. For instance an LCD panel in a system that
55 panel-timing:
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/Documentation/devicetree/bindings/hwmon/
Dadi,ltc2947.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nuno Sá <nuno.sa@analog.com>
15 https://www.analog.com/media/en/technical-documentation/data-sheets/LTC2947.pdf
20 - adi,ltc2947
33 adi,accumulator-ctl-pol:
35 This property controls the polarity of current that is accumulated to
40 datasheet for more information on the supported options.
41 $ref: /schemas/types.yaml#/definitions/uint32-array
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/Documentation/ABI/testing/
Dsysfs-class-pwm6 The pwm/ class sub-directory belongs to the Generic PWM
24 The number of PWM channels supported by the PWM chip.
32 Value is between 0 and /sys/class/pwm/pwmchipN/npwm - 1.
64 What: /sys/class/pwm/pwmchip<N>/pwmX/polarity
69 Sets the output polarity of the PWM signal to "normal" or
Dsysfs-timecard24 IRIG adjustments from external IRIG-B signal
42 IRIG signal is sent to the IRIG-B module
62 IRIG output is from the PHC, in IRIG-B format
106 Description: (RW) Specifies the number of seconds from 0-255 that the
118 Description: (RO) Specifies the signal duty cycle as a percentage from 1-99.
130 What: /sys/class/timecard/ocpN/genX/polarity
133 Description: (RO) Specifies the signal polarity, either 1 or 0.
157 period [duty [phase [polarity]]]
164 a percentage from 1-99. Polarity is 1 or 0.
168 period duty phase polarity start_time
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/Documentation/devicetree/bindings/gpio/
Dgpio-adnp.txt1 Avionic Design N-bit GPIO expander bindings
4 - compatible: should be "ad,gpio-adnp"
5 - reg: The I2C slave address for this device.
6 - interrupts: Interrupt specifier for the controllers interrupt.
7 - #gpio-cells: Should be 2. The first cell is the GPIO number and the
9 - bit 0: polarity (0: normal, 1: inverted)
10 - gpio-controller: Marks the device as a GPIO controller
11 - nr-gpios: The number of pins supported by the controller.
15 Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.
19 gpioext: gpio-controller@41 {
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Dgpio.txt5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
11 bindings use it, but are only supported for compatibility reasons and should not
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
44 recommended to use the two-cell approach.
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D8xxx_gpio.txt3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
12 controller, see bindings/interrupt-controller/interrupts.txt (the
18 nodes section in bindings/interrupt-controller/interrupts.txt for
22 - compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio"
23 for 83xx, "fsl,mpc8572-gpio" for 85xx, or
24 "fsl,mpc8610-gpio" for 86xx.
25 - #gpio-cells: Should be two. The first cell is the pin number
28 - interrupts: Interrupt mapping for GPIO IRQ.
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Dbrcm,brcmstb-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The controller's registers are organized as sets of eight 32-bit
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
22 - brcm,bcm7445-gpio
23 - const: brcm,brcmstb-gpio
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/Documentation/fb/
Dpxafb.rst10 modprobe pxafb options=vmem:2M,mode:640x480-8,passive
14 video=pxafb:vmem:2M,mode:640x480-8,passive
21 mode:XRESxYRES[-BPP]
74 outputen:POLARITY
76 Output Enable Polarity. 0 => active low, 1 => active high
78 pixclockpol:POLARITY
80 pixel clock polarity
87 PXA27x and later processors support overlay1 and overlay2 on-top of the
88 base framebuffer (although under-neath the base is also possible). They
89 support palette and no-palette RGB formats, as well as YUV formats (only
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/Documentation/devicetree/bindings/pinctrl/
Dbrcm,iproc-gpio.txt5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
23 - reg:
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Dbrcm,nsp-gpio.txt4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
11 - #gpio-cells:
14 bit[0]: polarity (0 for active high and 1 for active low)
16 - gpio-controller:
19 - ngpios:
20 Number of gpios supported (58x25 supports 32 and 58x23 supports 24)
23 - interrupts:
26 - interrupt-controller:
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/Documentation/hwmon/
Dds1621.rst4 Supported chips:
47 - Christian W. Zuckschwerdt <zany@triq.net>
48 - valuable contributions by Jan M. Sendler <sendler@sendler.de>
49 - ported to 2.6 by Aurelien Jarno <aurelien@aurel32.net>
53 ------------------
55 * polarity int
56 Output's polarity:
62 -----------
66 programmed into non-volatile on-chip registers). Temperature range is -55
68 Fahrenheit range of -67 to +257 degrees with 0.9 steps. If polarity
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/Documentation/userspace-api/media/v4l/
Dvidioc-g-dv-timings.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_G_DV_TIMINGS - VIDIOC_S_DV_TIMINGS - VIDIOC_SUBDEV_G_DV_TIMINGS - VIDIOC_SUBDEV_S_DV_TIMINGS…
52 structure as argument. If the ioctl is not supported or the timing
56 registered in read-only mode is not allowed. An error is returned and the errno
57 variable is set to ``-EPERM``.
59 The ``linux/v4l2-dv-timings.h`` header can be used to get the timings of
68 On success 0 is returned, on error -1 and the ``errno`` variable is set
70 :ref:`Generic Error Codes <gen-errors>` chapter.
73 This ioctl is not supported, or the :ref:`VIDIOC_S_DV_TIMINGS <VIDIOC_G_DV_TIMINGS>`
77 Digital video timings are not supported for this input or output.
[all …]
/Documentation/devicetree/bindings/sound/
Dnuvoton,nau8825.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Hsu <KCHSU0@nuvoton.com>
13 - $ref: dai-common.yaml#
18 - nuvoton,nau8825
26 nuvoton,jkdet-enable:
31 nuvoton,jkdet-pull-enable:
34 If set - pin pull enabled, otherwise pin in high impedance state.
37 nuvoton,jkdet-pull-up:
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Dnuvoton,nau8824.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Hsu <KCHSU0@nuvoton.com>
13 - $ref: dai-common.yaml#
18 - nuvoton,nau8824
23 '#sound-dai-cells':
28 - description: The phandle of the master clock to the CODEC
30 clock-names:
32 - const: mclk
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/Documentation/devicetree/bindings/interrupt-controller/
Dbrcm,bcm6345-l1-intc.txt1 Broadcom BCM6345-style Level 1 interrupt controller
8 - 32, 64 or 128 incoming level IRQ lines
10 - Most onchip peripherals are wired directly to an L1 input
12 - A separate instance of the register set for each CPU, allowing individual
15 - Contains one or more enable/status word pairs per CPU
17 - No atomic set/clear operations
19 - No polarity/level/edge settings
21 - No FIFO or priority encoder logic; software is expected to read all
22 2-4 status words to determine which IRQs are pending
26 - compatible: should be "brcm,bcm<soc>-l1-intc", "brcm,bcm6345-l1-intc"
[all …]
Dbrcm,bcm7038-l1-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7038-style Level 1 interrupt controller
11 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
16 - 64, 96, 128, or 160 incoming level IRQ lines
18 - Most onchip peripherals are wired directly to an L1 input
20 - A separate instance of the register set for each CPU, allowing individual
23 - Atomic mask/unmask operations
[all …]
/Documentation/firmware-guide/acpi/
Dgpio-properties.rst1 .. SPDX-License-Identifier: GPL-2.0
31 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
34 Package () { "reset-gpios", Package () { ^BTH, 1, 1, 0 } },
35 Package () { "shutdown-gpios", Package () { ^BTH, 0, 0, 0 } },
40 The format of the supported GPIO property is::
61 In our Bluetooth example the "reset-gpios" refers to the second GpioIo()
68 and polarity settings. The table below shows the expectations:
70 +-------------+-------------+-----------------------------------------------+
71 | Pull Bias | Polarity | Requested... |
74 +-------------+-------------+-----------------------------------------------+
[all …]
/Documentation/spi/
Dspidev.rst5 SPI devices have a limited userspace API, supporting basic half-duplex
19 * Prototyping in an environment that's not crash-prone; stray pointers
33 The spidev driver contains lists of SPI devices that are supported for
36 The following are the SPI device tables supported by the spidev driver:
38 - struct spi_device_id spidev_spi_ids[]: list of devices that can be
42 - struct of_device_id spidev_dt_ids[]: list of devices that can be
46 - struct acpi_device_id spidev_acpi_ids[]: list of devices that can
52 post a patch for spidev to the linux-spi@vger.kernel.org mailing list.
54 It used to be supported to define an SPI device using the "spidev" name.
56 is no longer supported by the Linux kernel and instead a real SPI device
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