Searched full:polarity (Results 1 – 25 of 141) sorted by relevance
123456
| /Documentation/devicetree/bindings/media/i2c/ |
| D | tvp7002.txt | 10 - hsync-active: HSYNC Polarity configuration for the bus. Default value when
13 - vsync-active: VSYNC Polarity configuration for the bus. Default value when
16 - pclk-sample: Clock polarity of the bus. Default value when this property is
24 - field-even-active: Active-high Field ID output polarity control of the bus.
28 1 = FID output polarity inverted
|
| D | tvp514x.txt | 17 - hsync-active: HSYNC Polarity configuration for endpoint.
19 - vsync-active: VSYNC Polarity configuration for endpoint.
21 - pclk-sample: Clock polarity of the endpoint.
|
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | microchip,pic32-evic.txt | 9 External interrupts have a software configurable edge polarity. Non external
10 interrupts have a type and polarity that is determined by the source of the
26 irq_type - is used to describe the type and polarity of an interrupt. For
29 IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING to select the desired polarity.
34 polarity configuration. This array corresponds to the bits in the INTCON
49 and polarity.
|
| /Documentation/fb/ |
| D | viafb.modes | 25 # Polarity negative negative
50 # Polarity negative negative
71 # Polarity negative negative
92 # Polarity positive positive
113 # Polarity positive positive
134 # Polarity positive positive
155 # Polarity positive positive
176 # Polarity positive positive
197 # Polarity positive positive
219 # Polarity positive positive
[all …]
|
| D | pxafb.rst | 74 outputen:POLARITY
76 Output Enable Polarity. 0 => active low, 1 => active high
78 pixclockpol:POLARITY
80 pixel clock polarity
|
| /Documentation/devicetree/bindings/regulator/ |
| D | richtek,rtmv20-regulator.yaml | 100 richtek,strobe-polarity-high:
101 description: Strobe pin active polarity control.
104 richtek,vsync-polarity-high:
105 description: Vsync pin active polarity control.
150 richtek,strobe-polarity-high;
151 richtek,vsync-polarity-high;
|
| /Documentation/devicetree/bindings/net/ |
| D | airoha,en8811h.yaml | 13 The Airoha EN8811H PHY has the ability to reverse polarity
31 Reverse rx polarity of the SERDES. This is the receiving
37 Reverse tx polarity of SERDES. This is the transmitting
|
| /Documentation/devicetree/bindings/hwmon/ |
| D | ti,ina2xx.yaml | 69 ti,alert-polarity-active-high:
70 description: Alert pin is asserted based on the value of Alert polarity Bit
74 the alert polarity to active-high.
99 ti,alert-polarity-active-high;
|
| /Documentation/ABI/testing/ |
| D | sysfs-bus-iio-adc-stm32 | 13 Reading returns current trigger polarity.
15 Writing value before enabling conversions sets trigger polarity.
|
| /Documentation/devicetree/bindings/extcon/ |
| D | wlf,arizona.yaml | 42 Invert the polarity of the jack detection switch.
58 GPIO specifier for the GPIO controlling the headset polarity if one
96 Headset polarity configurations (generally used for detection of
99 represents one polarity configuration.
|
| /Documentation/devicetree/bindings/iio/addac/ |
| D | adi,ad74115.yaml | 225 adi,ext1-burnout-current-polarity-sourcing:
228 When not present, the burnout current polarity for EXT1 is sinking.
229 When present, the burnout current polarity for EXT1 is sourcing.
240 adi,ext2-burnout-current-polarity-sourcing:
243 When not present, the burnout current polarity for EXT2 is sinking.
244 When present, the burnout current polarity for EXT2 is sourcing.
255 adi,viout-burnout-current-polarity-sourcing:
258 When not present, the burnout current polarity for VIOUT is sinking.
259 When present, the burnout current polarity for VIOUT is sourcing.
|
| /Documentation/driver-api/ |
| D | pwm.rst | 84 period). struct pwm_args contains 2 fields (period and polarity) and should
125 polarity
126 Changes the polarity of the PWM signal (read/write).
128 the polarity.
153 When implementing polarity support in a PWM driver, make sure to respect the
154 signal conventions in the PWM framework. By definition, normal polarity
157 polarity starts low for the duration of the duty cycle and goes high for the
|
| /Documentation/devicetree/bindings/gpio/ |
| D | gpio.txt | 86 A gpio-specifier should contain a flag indicating the GPIO polarity; active-
90 The gpio-specifier's polarity flag should represent the physical level at the
97 When the device's signal polarity is configurable, the binding for the
100 a) Define a single static polarity for the signal, with the expectation that
102 that signal polarity.
104 The static choice of polarity may be either:
112 In particular, the polarity cannot be derived from the gpio-specifier, since
114 concepts of configurable signal polarity in the device, and possible board-
119 b) Pick a single option for device signal polarity, and document this choice
120 in the binding. The gpio-specifier should represent the polarity of the signal
[all …]
|
| /Documentation/devicetree/bindings/thermal/ |
| D | rockchip-thermal.yaml | 69 rockchip,hw-tshut-polarity:
70 description: The hardware-controlled active polarity 0:LOW 1:HIGH.
100 rockchip,hw-tshut-polarity = <0>;
|
| /Documentation/devicetree/bindings/display/ti/ |
| D | ti,omap2-dss.txt | 57 - ti,invert-polarity: invert the polarity of the video signal
|
| D | ti,omap3-dss.txt | 68 - ti,invert-polarity: invert the polarity of the video signal
|
| /Documentation/devicetree/bindings/power/supply/ |
| D | summit,smb347-charger.yaml | 76 summit,inok-polarity:
78 Polarity of INOK signal indicating presence of external power supply.
91 description: INOK signal is fixed and polarity needs to be toggled
157 summit,inok-polarity = <SMB3XX_SYSOK_INOK_ACTIVE_LOW>;
|
| /Documentation/devicetree/bindings/pinctrl/ |
| D | canaan,k210-fpioa.yaml | 122 input-polarity-invert:
125 Enable or disable pin input polarity inversion.
135 output-polarity-invert:
138 Enable or disable pin output polarity inversion.
|
| /Documentation/hwmon/ |
| D | ds1621.rst | 55 * polarity int
56 Output's polarity:
68 Fahrenheit range of -67 to +257 degrees with 0.9 steps. If polarity
71 As for the thermostat, behavior can also be programmed using the polarity
77 is somewhat misleading in this point since setting the polarity bit does
|
| /Documentation/devicetree/bindings/mmc/ |
| D | mmc-controller.yaml | 52 # *NOTE* on CD and WP polarity. To use common for all SD/MMC host
53 # controllers line polarity properties, we have to fix the meaning
62 # as dedicated pins. Polarity of dedicated pins can be specified,
63 # using *-inverted properties. GPIO polarity can also be specified
69 # double-inversion and actually means the "normal" line polarity is
74 The Write Protect line polarity is inverted.
79 The CD line polarity is inverted.
|
| D | atmel,sama5d2-sdhci.yaml | 51 When present, polarity on the SDCAL SoC pin is inverted. The default
52 polarity for this signal is described in the datasheet. For instance on
|
| /Documentation/devicetree/bindings/pwm/ |
| D | pwm.txt | 48 - PWM_POLARITY_INVERTED: invert the PWM signal polarity
50 Example with optional PWM specifier for inverse polarity
|
| /Documentation/devicetree/bindings/sound/ |
| D | nuvoton,nau8821.yaml | 43 nuvoton,jkdet-polarity:
44 description: JKDET pin polarity.
138 nuvoton,jkdet-polarity = <GPIO_ACTIVE_LOW>;
|
| /Documentation/devicetree/bindings/usb/ |
| D | fsl,usb2.yaml | 54 port power polarity of internal PHY signal DRVVBUS is inverted.
60 the PWR_FAULT signal polarity is inverted.
|
| /Documentation/devicetree/bindings/serial/ |
| D | 8250.yaml | 22 - aspeed,sirq-polarity-sense
197 aspeed,sirq-polarity-sense:
201 offset and bit number to identify how the SIRQ polarity should be
218 polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only
|
123456