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/Documentation/ABI/testing/
Dconfigfs-rdma_cm1 What: /config/rdma_cm
4 Description: Interface is used to configure RDMA-cable HCAs in respect to
5 RDMA-CM attributes.
8 configfs in /config directory use:
9 # mount -t configfs none /config/
13 mkdir -p /config/rdma_cm/<hca>
16 What: /config/rdma_cm/<hca>/ports/<port-num>/default_roce_mode
19 Description: RDMA-CM based connections from HCA <hca> at port <port-num>
24 What: /config/rdma_cm/<hca>/ports/<port-num>/default_roce_tos
27 Description: RDMA-CM QPs from HCA <hca> at port <port-num>
[all …]
Dconfigfs-usb-gadget-acm1 What: /config/usb-gadget/gadget/functions/acm.name
7 It contains the port number of the /dev/ttyGS<n> device
10 What: /config/usb-gadget/gadget/functions/acm.name/protocol
Dconfigfs-usb-gadget-obex1 What: /config/usb-gadget/gadget/functions/obex.name
7 It contains the port number of the /dev/ttyGS<n> device
Dconfigfs-usb-gadget-serial1 What: /config/usb-gadget/gadget/functions/gser.name
7 It contains the port number of the /dev/ttyGS<n> device
/Documentation/admin-guide/perf/
Dhns3-pmu.rst30 The "format" directory describes all formats of the config (events) and
44 config=0x00204
46 config=0x10204
51 The bits 0~15 of config (here 0x0204) are the true hardware event code. If
52 two events have same value of bits 0~15 of config, that means they are
53 event pair. And the bit 16 of config indicates getting counter 0 or
64 filter mode supported: global/port/port-tc/func/func-queue/
71 ------------------------------------------
73 …$# perf stat -g -e hns3_pmu_sicl_0/bw_ssu_rpu_byte_num,global=1/ -e hns3_pmu_sicl_0/bw_ssu_rpu_tim…
75 …$# perf stat -g -e hns3_pmu_sicl_0/config=0x00002,global=1/ -e hns3_pmu_sicl_0/config=0x10002,glob…
[all …]
Darm-ccn.rst5 CCN-504 is a ring-bus interconnect consisting of 11 crosspoints
11 -----------------
17 The "format" directory describes format of the config, config1
29 Crosspoint watchpoint-based events (special "event" value 0xfe)
30 require "xp" and "vc" as above plus "port" (device port index),
35 (due to limited number of the config values) in the "cmp_mask"
45 request the events on this processor (if not, the perf_event->cpu value
54 ccn/xp_valid_flit,xp=?,port=?,vc=?,dir=?/ [Kernel PMU event]
57 / # perf stat -a -e ccn/cycles/,ccn/xp_valid_flit,xp=1,port=0,vc=1,dir=1/ \
61 not work. Per-task (without "-a") perf sessions are not supported.
Dcxl.rst1 .. SPDX-License-Identifier: GPL-2.0
10 CXL components (e.g. Root Port, Switch Upstream Port, End Point) may have
34 The "format" directory describes all formats of the config (event vendor id,
41 multiple mask bits in config. For example, all Device to Host Read Requests
58 -----------------------------------------------------------
60 $# perf stat -a -e cxl_pmu_mem0.0/clock_ticks/ -e cxl_pmu_mem0.0/d2h_req_rdshared/
64 $# perf stat -a -e cxl_pmu_mem0.0/vid=VID,gid=GID,mask=MASK/
67 It only supports system-wide counting so attaching to a task is
/Documentation/devicetree/bindings/sound/
Dimx-audmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/imx-audmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Oleksij Rempel <o.rempel@pengutronix.de>
15 - items:
16 - enum:
17 - fsl,imx27-audmux
18 - const: fsl,imx21-audmux
19 - items:
[all …]
/Documentation/hwmon/
Dsmsc47b397.rst6 * SMSC LPC47B397-NC
8 * SMSC SCH5307-NS
14 Addresses scanned: none, address read from Super I/O config space
20 - Mark M. Hoffman <mhoffman@lightlink.com>
21 - Utilitek Systems, Inc.
25 The following specification describes the SMSC LPC47B397-NC [1]_ sensor chip
27 provided by Craig Kelly (In-Store Broadcast Network) and edited/corrected
30 .. [1] And SMSC SCH5307-NS and SCH5317, which have different device IDs but are
33 -------------------------------------------------------------------------
36 -------------------------------------------------------------------------
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/Documentation/watchdog/
Dwatchdog-parameters.rst7 be listed here unless the driver has its own driver-specific information
10 See Documentation/admin-guide/kernel-parameters.rst for information on
14 -------------------------------------------------
21 timeout. Setting this to a non-zero value can be useful to ensure that
25 -------------------------------------------------
29 Acquire WDT 'stop' io port (default 0x43)
31 Acquire WDT 'start' io port (default 0x443)
34 (default=kernel config parameter)
36 -------------------------------------------------
40 Advantech WDT 'stop' io port (default 0x443)
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/Documentation/networking/
Dnetconsole.rst1 .. SPDX-License-Identifier: GPL-2.0
10 2.6 port and netpoll api by Matt Mackall <mpm@selenic.com>, Sep 9 2003
29 It can be used either built-in or as a module. As a built-in,
41 netconsole=[+][r][src-port]@[src-ip]/[<dev>],[tgt-port]@<tgt-ip>/[tgt-macaddr]
46 src-port source for UDP packets (defaults to 6665)
47 src-ip source IP to use (interface address)
49 tgt-port port for logging agent (6666)
50 tgt-ip IP address for logging agent
51 tgt-macaddr ethernet MAC address for logging agent (broadcast)
71 Built-in netconsole starts immediately after the TCP stack is
[all …]
/Documentation/devicetree/bindings/pci/
Damlogic,axg-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/amlogic,axg-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
16 - $ref: /schemas/pci/pci-host-bridge.yaml#
17 - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
19 # We need a select here so we don't match all nodes with 'snps,dw-pcie'
24 - amlogic,axg-pcie
25 - amlogic,g12a-pcie
[all …]
Dmobiveil-pcie.txt1 * Mobiveil AXI PCIe Root Port Bridge DT description
3 Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP
7 - #address-cells: Address representation for root ports, set to <3>
8 - #size-cells: Size representation for root ports, set to <2>
9 - #interrupt-cells: specifies the number of cells needed to encode an
11 - compatible: Should contain "mbvl,gpex40-pcie"
12 - reg: Should contain PCIe registers location and length
15 "csr_axi_slave" : Bridge config registers
20 - device_type: must be "pci"
21 - apio-wins : number of requested apio outbound windows
[all …]
Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
[all …]
Dhisilicon-histb-pcie.txt6 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
11 - compatible: Should be one of the following strings:
12 "hisilicon,hi3798cv200-pcie"
13 - reg: Should contain sysctl, rc_dbi, config registers location and length.
14 - reg-names: Must include the following entries:
16 "rc-dbi": configuration space of PCIe controller;
17 "config": configuration transaction space of PCIe controller.
18 - bus-range: PCI bus numbers covered.
19 - interrupts: MSI interrupt.
20 - interrupt-names: Must include "msi" entries.
[all …]
/Documentation/driver-api/tty/
Dn_gsm.rst10 https://www.3gpp.org/ftp/Specs/archive/07_series/07.10/0710-720.zip
13 modems connected to a physical serial port.
18 Config Initiator
19 ----------------
22 its serial port. Depending on the modem used, you can pass more or less
32 #. Configure DLCs using ``GSMIOC_GETCONF_DLCI``/``GSMIOC_SETCONF_DLCI`` ioctl for non-defaults.
34 #. Obtain base gsmtty number for the used serial port.
37 (a good starting point is util-linux-ng/sys-utils/ldattach.c)::
54 /* open the serial port connected to the modem */
57 /* configure the serial port : speed, flow control ... */
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx27-pinctrl.txt4 - compatible: "fsl,imx27-iomuxc"
9 - fsl,pins: three integers array, represents a group of pins mux and config
10 setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
13 configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
14 number on the specific port (between 0 and 31).
21 0 - Primary function
22 1 - Alternate function
23 2 - GPIO
28 0 - Input
29 1 - Output
[all …]
/Documentation/PCI/
Dpciebus-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
5 The PCI Express Port Bus Driver Guide HOWTO
14 This guide describes the basics of the PCI Express Port Bus driver
16 register/unregister with the PCI Express Port Bus Driver.
19 What is the PCI Express Port Bus Driver
22 A PCI Express Port is a logical PCI-PCI Bridge structure. There
23 are two types of PCI Express Port: the Root Port and the Switch
24 Port. The Root Port originates a PCI Express link from a PCI Express
25 Root Complex and the Switch Port connects PCI Express links to
26 internal logical PCI buses. The Switch Port, which has its secondary
[all …]
Dsysfs-pci.rst1 .. SPDX-License-Identifier: GPL-2.0
11 |-- 0000:17:00.0
12 | |-- class
13 | |-- config
14 | |-- device
15 | |-- enable
16 | |-- irq
17 | |-- local_cpus
18 | |-- remove
19 | |-- resource
[all …]
/Documentation/devicetree/bindings/display/bridge/
Dintel,keembay-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/intel,keembay-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anitha Chrisanthus <anitha.chrisanthus@intel.com>
11 - Edmond J Dea <edmund.j.dea@intel.com>
15 const: intel,keembay-dsi
19 - description: MIPI registers range
21 reg-names:
23 - const: mipi
[all …]
/Documentation/dev-tools/
Dkgdb.rst15 Kdb is simplistic shell-style interface which you can use on a system
22 kernel built-ins or in kernel modules if the code was built with
40 kgdb I/O modules compiled as built-ins or loadable kernel modules in the
46 - In order to enable compilation of kdb, you must first enable kgdb.
48 - The kgdb test compile options are described in the kgdb test suite
51 Kernel config options for kgdb
52 ------------------------------
55 :menuselection:`Kernel hacking --> Kernel debugging` and select
61 :menuselection:`Compile the kernel with debug info` in the config menu.
65 the kernel with frame pointers` in the config menu. This option inserts code
[all …]
/Documentation/arch/x86/
Dearlyprintk.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Mini-HOWTO for using the earlyprintk=dbgp boot option with a
8 USB2 Debug port key and a debug cable, on x86 systems.
13 [host/target] <-------> [USB debug key] <-------> [client/console]
18 a) Host/target system needs to have USB debug port capability.
20 You can check this capability by looking at a 'Debug port' bit in
21 the lspci -vvv output::
23 # lspci -vvv
25 …roller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 (rev 03) (prog-if 20 [EHCI])
27 …Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisIN…
[all …]
/Documentation/ABI/stable/
Dsysfs-bus-usb8 not the "USB-Persist" facility is enabled for the device. For
12 For more information, see Documentation/driver-api/usb/persist.rst.
27 The autosuspend delay for newly-created devices is set to
37 connected to the machine. This file is read-only.
49 active, i.e. not in a suspended state. This file is read-only.
63 What: /sys/bus/usb/devices/<busnum>-<port[.port]>...:<config num>-<interface num>/supports_autosus…
77 git://git.moblin.org/users/sarah/usb-pm-tool/
101 device. Writing 0 or -1 to bConfigurationValue will reset the
110 Writing -1 will always unconfigure the device.
117 Bus-number of the USB-bus the device is connected to.
[all …]
/Documentation/arch/powerpc/
Dmpc52xx.rst9 - U-Boot::
16 then, on U-boot:
21 - DBug::
31 DBug> dn -i zImage.initrd.lite5200
36 - The port is named mpc52xxx, and config options are PPC_MPC52xx. The MGT5100
41 - Of course, I inspired myself from the 2.4 port. If you think I forgot to
/Documentation/devicetree/bindings/usb/
Dchipidea,usb2-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
25 clock-names:
31 power-domains:
37 reset-names:
40 "#reset-cells":
45 itc-setting:
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