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/Documentation/devicetree/bindings/net/
Dmarvell,pp2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/marvell,pp2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcin Wojtas <mw@semihalf.com>
11 - Russell King <linux@armlinux.org>
21 - marvell,armada-375-pp2
22 - marvell,armada-7k-pp22
28 "#address-cells":
31 "#size-cells":
[all …]
Dfsl,fman-port.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Frame Manager Port Device
10 - Frank Li <Frank.Li@nxp.com>
21 - fsl,fman-v2-port-oh
22 - fsl,fman-v2-port-rx
23 - fsl,fman-v2-port-tx
24 - fsl,fman-v3-port-oh
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Dhisilicon-hns-nic.txt4 - compatible: "hisilicon,hns-nic-v1" or "hisilicon,hns-nic-v2".
5 "hisilicon,hns-nic-v1" is for hip05.
6 "hisilicon,hns-nic-v2" is for Hi1610 and Hi1612.
7 - ae-handle: accelerator engine handle for hns,
9 see Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
10 - port-id: is the index of port provided by DSAF (the accelerator). DSAF can
11 connect to 8 PHYs. Port 0 to 1 are both used for administration purpose. They
17 port-id can be 2 to 7. Here is the diagram:
18 +-----+---------------+
20 +-+-+-+---+-+-+-+-+-+-+
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/Documentation/devicetree/bindings/display/bridge/
Dfsl,imx8qxp-pixel-link.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
27 - fsl,imx8qm-dc-pixel-link
28 - fsl,imx8qxp-dc-pixel-link
30 fsl,dc-id:
36 fsl,dc-stream-id:
47 port@0:
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Dfsl,imx8qxp-pxl2dpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
14 interfaces the pixel link 36-bit data output and the DSI controller’s
15 MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
25 const: fsl,imx8qxp-pxl2dpi
27 fsl,sc-resource:
29 description: The SCU resource ID associated with this PXL2DPI instance.
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Dlontium,lt9211.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/lontium,lt9211.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
13 The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS
14 or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI.
19 - lontium,lt9211
27 reset-gpios:
31 vccio-supply:
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/Documentation/netlink/specs/
Ddevlink.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
5 protocol: genetlink-legacy
10 -
12 name: sb-pool-type
14 -
16 -
18 -
20 name: port-type
22 -
24 -
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/Documentation/devicetree/bindings/i2c/
Di2c-opal.txt1 Device-tree bindings for I2C OPAL driver
2 ----------------------------------------
5 used by the firmware itself for configuring the port. From the linux
6 perspective, the properties of use are "ibm,port-name" and "ibm,opal-id".
10 - reg: Port-id within a given master
11 - compatible: must be "ibm,opal-i2c"
12 - ibm,opal-id: Refers to a specific bus and used to identify it when calling
14 - bus-frequency: Operating frequency of the i2c bus (in HZ). Informational for
18 - ibm,port-name: Firmware provides this name that uniquely identifies the i2c
19 port.
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/Documentation/arch/s390/
Dqeth.rst5 OSA and HiperSockets Bridge Port Support
9 -------
12 a primary or a secondary Bridge Port. For more information, see
13 "z/VM Connectivity, SC24-6174".
15 When run on an OSA or HiperSockets Bridge Capable Port hardware, and the state
16 of some configured Bridge Port device on the channel changes, a udev
21 indicates that the Bridge Port device changed
25 the role assigned to the port.
28 the newly assumed state of the port.
30 When run on HiperSockets Bridge Capable Port hardware with host address
[all …]
/Documentation/devicetree/bindings/ata/
Dpata-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/pata-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
18 The PATA (IDE) controller-specific device tree bindings are responsible for
28 "#address-cells":
31 "#size-cells":
35 "^ide-port@[0-1]$":
38 ID number 0 and the slave drive will have ID number 1. The PATA port
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Dsata-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/sata-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
18 The SATA controller-specific device tree bindings are responsible for
28 "#address-cells":
31 "#size-cells":
34 dma-coherent: true
37 "^sata-port@[0-9a-e]$":
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Dahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
24 - $ref: sata-common.yaml#
32 reg-names:
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/Documentation/devicetree/bindings/extcon/
Dextcon-usbc-cros-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/extcon/extcon-usbc-cros-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ChromeOS EC USB Type-C cable and accessories detection
10 - Benson Leung <bleung@chromium.org>
16 The node for this device must be under a cros-ec node like google,cros-ec-spi
17 or google,cros-ec-i2c.
21 const: google,extcon-usbc-cros-ec
23 google,usb-port-id:
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/Documentation/admin-guide/perf/
Dhns3-pmu.rst17 The HNS3 PMU driver registers a perf PMU with the name of its sicl id.::
64 filter mode supported: global/port/port-tc/func/func-queue/
71 ------------------------------------------
73 …$# perf stat -g -e hns3_pmu_sicl_0/bw_ssu_rpu_byte_num,global=1/ -e hns3_pmu_sicl_0/bw_ssu_rpu_tim…
75 …$# perf stat -g -e hns3_pmu_sicl_0/config=0x00002,global=1/ -e hns3_pmu_sicl_0/config=0x10002,glob…
79 --------------
86 $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,global=1/ -I 1000
88 2. port mode
89 PMU collect performance statistic of one whole physical port. The port id
90 is same as mac id. The "tc" filter option must be set to 0xF in this mode,
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/Documentation/networking/dsa/
Ddsa.rst19 they configured/queried a switch port network device or a regular network
22 An Ethernet switch typically comprises multiple front-panel ports and one
24 presence of a management port connected to an Ethernet controller capable of
27 gateways, or even top-of-rack switches. This host Ethernet controller will
36 For each front-panel port, DSA creates specialized network devices which are
37 used as controlling and data-flowing endpoints for use by the Linux networking
46 - what port is this frame coming from
47 - what was the reason why this frame got forwarded
48 - how to send CPU originated traffic to specific ports
52 on Port-based VLAN IDs).
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/Documentation/ABI/testing/
Dsysfs-platform-dfl-port1 What: /sys/bus/platform/devices/dfl-port.0/id
5 Description: Read-only. It returns id of this port. One DFL FPGA device
6 may have more than one port. Userspace could use this id to
9 What: /sys/bus/platform/devices/dfl-port.0/afu_id
13 Description: Read-only. User can program different PR bitstreams to FPGA
18 What: /sys/bus/platform/devices/dfl-port.0/power_state
22 Description: Read-only. It reports the APx (AFU Power) state, different APx
24 returns "0" - Normal / "1" - AP1 / "2" - AP2 / "6" - AP6.
26 What: /sys/bus/platform/devices/dfl-port.0/ap1_event
30 Description: Read-write. Read this file for AP1 (AFU Power State 1) event.
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Dsysfs-devices-platform-kunpeng_hccs9 contains read-only attributes exposing some summarization
32 contains read-only attributes exposing some summarization
34 The Y in 'dieY' indicates the hardware id of the die on chip who
35 has chip id X.
60 contains read-only attributes exposing information about
61 a HCCS port. The N value in 'hccsN' indicates this port id.
62 The X in 'chipX' indicates the ID of the chip to which the
63 HCCS port belongs. For example, X ranges from to 'n - 1' if the
65 The Y in 'dieY' indicates the hardware id of the die to which
66 the hccs port belongs.
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Dsysfs-bus-intel_th-output-devices1 What: /sys/bus/intel_th/devices/<intel_th_id>-<device><id>/active
7 correstponding output port driver be loaded.
9 What: /sys/bus/intel_th/devices/<intel_th_id>-msc<msc-id>/port
13 Description: (RO) Port number, corresponding to this output device on the
15 port driver is not loaded.
Dsysfs-firmware-sgi_uv8 Under that directory are a number of read-only attributes::
18 is used to select arch-dependent addresses and features.
29 The partition_id entry contains the partition id.
33 partition id.
35 The coherence_id entry contains the coherence id.
37 domains. The coherence id indicates which coherence domain
59 Each hub object directory contains a number of read-only attributes::
69 If a cnode value is not applicable, the value returned will be -1.
86 If a nasid value is not applicable, the value returned will be -1.
94 Each hub object directory also contains a number of port objects,
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/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-vip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Luca Ceresoli <luca.ceresoli@bootlin.com>
15 - nvidia,tegra20-vip
21 port@0:
22 $ref: /schemas/graph.yaml#/properties/port
24 Port receiving the video stream from the sensor
26 port@1:
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/Documentation/devicetree/bindings/net/dsa/
Dnxp,sja1105.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
16 - Vladimir Oltean <vladimir.oltean@nxp.com>
21 - nxp,sja1105e
22 - nxp,sja1105t
23 - nxp,sja1105p
24 - nxp,sja1105q
[all …]
Dmarvell,mv88e6xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/marvell,mv88e6xxx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
16 can investigate switch ID registers to find out which actual version
22 - enum:
23 - marvell,mv88e6085
24 - marvell,mv88e6190
25 - marvell,mv88e6250
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/Documentation/devicetree/bindings/phy/
Drockchip,inno-usb2phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk3128-usb2phy
17 - rockchip,rk3228-usb2phy
18 - rockchip,rk3308-usb2phy
19 - rockchip,rk3328-usb2phy
[all …]
/Documentation/devicetree/bindings/media/
Dvideo-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/media/video-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
15 received on the active input port is passed through to the output port. Muxes
20 const: video-mux
22 mux-controls:
25 '#address-cells':
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/Documentation/devicetree/bindings/sound/
Dqcom,wcd937x-sdw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,wcd937x-sdw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9370/WCD9375 Codec is a standalone Hi-Fi audio codec IC.
24 qcom,tx-port-mapping:
26 Specifies static port mapping between device and host tx ports.
27 In the order of the device port index which are adc1_port, adc23_port,
31 WCD9370 TX Port 1 (ADC1) <=> SWR2 Port 2
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