Searched +full:port +full:- +full:mapping (Results 1 – 25 of 136) sorted by relevance
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| /Documentation/devicetree/bindings/sound/ |
| D | qcom,wcd937x-sdw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,wcd937x-sdw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9370/WCD9375 Codec is a standalone Hi-Fi audio codec IC.
24 qcom,tx-port-mapping:
26 Specifies static port mapping between device and host tx ports.
27 In the order of the device port index which are adc1_port, adc23_port,
31 WCD9370 TX Port 1 (ADC1) <=> SWR2 Port 2
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| D | qcom,wcd939x-sdw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,wcd939x-sdw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9390/WCD9395 Codec is a standalone Hi-Fi audio codec IC.
23 qcom,tx-port-mapping:
25 Specifies static port mapping between device and host tx ports.
26 In the order of the device port index.
27 $ref: /schemas/types.yaml#/definitions/uint32-array
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| D | qcom,wcd938x-sdw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,wcd938x-sdw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9380/WCD9385 Codec is a standalone Hi-Fi audio codec IC.
24 qcom,tx-port-mapping:
26 Specifies static port mapping between slave and master tx ports.
27 In the order of slave port index.
28 $ref: /schemas/types.yaml#/definitions/uint32-array
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| D | qcom,wcd939x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9390/WCD9395 Codec is a standalone Hi-Fi audio codec IC.
15 The WCD9390/WCD9395 IC has a functionally separate USB-C Mux subsystem
17 The Audio Headphone and Microphone data path between the Codec and the USB-C Mux
18 subsystems are external to the IC, thus requiring DT port-endpoint graph description
19 to handle USB-C altmode & orientation switching for Audio Accessory Mode.
22 - $ref: dai-common.yaml#
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| D | qcom,wsa8840.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
18 - $ref: dai-common.yaml#
27 powerdown-gpios:
31 reset-gpios:
35 qcom,port-mapping:
37 Specifies static port mapping between slave and master ports.
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| D | qcom,wsa883x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
19 - $ref: dai-common.yaml#
28 powerdown-gpios:
32 vdd-supply:
35 qcom,port-mapping:
37 Specifies static port mapping between slave and master ports.
38 In the order of slave port index.
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| D | qcom,wcd938x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9380/WCD9385 Codec is a standalone Hi-Fi audio codec IC.
17 - $ref: dai-common.yaml#
18 - $ref: qcom,wcd93xx-common.yaml#
23 - qcom,wcd9380-codec
24 - qcom,wcd9385-codec
26 us-euro-gpios:
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| /Documentation/devicetree/bindings/display/panel/ |
| D | advantech,idk-2121wr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/advantech,idk-2121wr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Advantech IDK-2121WR 21.5" Full-HD dual-LVDS panel
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The IDK-2121WR from Advantech is a Full-HD dual-LVDS panel.
15 A dual-LVDS interface is a dual-link connection with even pixels traveling
18 The panel expects odd pixels on the first port, and even pixels on the
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| D | sgd,gktw70sdae4se.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: panel-common.yaml#
15 - $ref: /schemas/display/lvds.yaml#
24 - compatible
29 - const: sgd,gktw70sdae4se
30 - const: panel-lvds
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| D | advantech,idk-1110wr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/advantech,idk-1110wr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Advantech IDK-1110WR 10.1" WSVGA LVDS Display Panel
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: panel-common.yaml#
15 - $ref: /schemas/display/lvds.yaml#
21 const: advantech,idk-1110wr
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| D | mitsubishi,aa104xd12.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: panel-common.yaml#
15 - $ref: /schemas/display/lvds.yaml#
24 - compatible
29 - const: mitsubishi,aa104xd12
30 - const: panel-lvds
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| D | mitsubishi,aa121td01.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: panel-common.yaml#
15 - $ref: /schemas/display/lvds.yaml#
24 - compatible
29 - const: mitsubishi,aa121td01
30 - const: panel-lvds
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| D | innolux,ee101ia-01d.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/innolux,ee101ia-01d.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Innolux Corporation 10.1" EE101IA-01D WXGA (1280x800) LVDS panel
10 - Heiko Stuebner <heiko.stuebner@bq.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: panel-common.yaml#
15 - $ref: /schemas/display/lvds.yaml#
21 const: innolux,ee101ia-01d
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | cpus.txt | 13 - fsl,eref-*
19 by the Power ISA. For these EREF-specific categories, the existence of
20 a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
24 - fsl,portid-mapping
27 Definition: The Coherency Subdomain ID Port Mapping Registers and
28 Snoop ID Port Mapping registers, which are part of the CoreNet
30 ID/CoreNet Snoop ID to cpu mapping functions. Certain bits from
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| D | ccf.txt | 5 The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure
10 - compatible: <string list>
11 fsl,corenet1-cf - CoreNet coherency fabric version 1.
14 fsl,corenet2-cf - CoreNet coherency fabric version 2.
17 fsl,corenet-cf - Used to represent the common registers
22 "fsl,corenet1-cf" or "fsl,corenet2-cf".
24 - reg: <prop-encoded-array>
27 - interrupts: <prop-encoded-array>
28 Interrupt mapping for CCF error interrupt.
30 - fsl,ccf-num-csdids: <u32>
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| /Documentation/devicetree/bindings/display/imx/ |
| D | ldb.txt | 1 Device-Tree bindings for LVDS Display Bridge (ldb)
6 The LVDS Display Bridge device tree node contains up to two lvds-channel
10 - #address-cells : should be <1>
11 - #size-cells : should be <0>
12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
16 - gpr : should be <&gpr> on i.MX53 and i.MX6q.
17 The phandle points to the iomuxc-gpr region containing the LVDS
19 - clocks, clock-names : phandles to the LDB divider and selector clocks and to
21 Documentation/devicetree/bindings/clock/clock-bindings.txt
23 "di0_pll" - LDB LVDS channel 0 mux
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | lvds-codec.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/lvds-codec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
16 LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
21 [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
28 Those devices have been marketed under the FPD-Link and FlatLink brand names
34 - items:
35 - enum:
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| /Documentation/devicetree/bindings/power/supply/ |
| D | gpio-charger.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/supply/gpio-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
19 const: gpio-charger
21 charger-type:
23 - unknown
24 - battery
25 - ups
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| /Documentation/devicetree/bindings/net/ |
| D | cavium-pip.txt | 10 - compatible: "cavium,octeon-3860-pip"
14 - reg: The base address of the PIP's register bank.
16 - #address-cells: Must be <1>.
18 - #size-cells: Must be <0>.
21 - compatible: "cavium,octeon-3860-pip-interface"
25 - reg: The interface number.
27 - #address-cells: Must be <1>.
29 - #size-cells: Must be <0>.
31 Properties for PIP port which is a child the PIP interface:
32 - compatible: "cavium,octeon-3860-pip-port"
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| /Documentation/devicetree/bindings/pci/ |
| D | pci.txt | 3 PCI Bus Binding to: IEEE Std 1275-1994
4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
6 And for the interrupt mapping part:
8 Open Firmware Recommended Practice: Interrupt Mapping
9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
14 - linux,pci-domain:
21 - max-link-speed:
27 - reset-gpios:
30 - supports-clkreq:
32 root port to downstream device and host bridge drivers can do programming
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| /Documentation/core-api/ |
| D | cachetlb.rst | 25 virtual-->physical address translations obtained from the software
59 modifications for the address space 'vma->vm_mm' in the range
60 'start' to 'end-1' will be visible to the cpu. That is, after
62 virtual addresses in the range 'start' to 'end-1'.
67 The interface is provided in hopes that the port can find
78 address space is available via vma->vm_mm. Also, one may
79 test (vma->vm_flags & VM_EXEC) to see if this region is
81 split-tlb type setups).
84 page table modification for address space 'vma->vm_mm' for
87 'vma->vm_mm' for virtual address 'addr'.
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| /Documentation/devicetree/bindings/gpio/ |
| D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
42 implemented by the SoC. Each GPIO is assigned to a port, and a port may
44 alphabetical port name and an integer GPIO name within the port. For
48 of implemented GPIOs within each port varies. GPIO registers within a
49 controller are grouped and laid out according to the port they affect.
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| /Documentation/devicetree/bindings/ata/ |
| D | fsl-sata.txt | 3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA port should have its own node.
7 - compatible : compatible list, contains 2 entries, first is
8 "fsl,CHIP-sata", where CHIP is the processor
10 "fsl,pq-sata"
11 - interrupts : <interrupt mapping for SATA IRQ>
12 - cell-index : controller index.
19 - reg : <registers mapping>
23 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
25 cell-index = <1>;
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | qca8k.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
14 describing a port needs to have a valid phandle referencing the internal PHY
15 it is connected to. This is because there is no N:N mapping of port and PHY
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17 the switch node and declare the phandle for the port, referencing the internal
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | qcom,pdc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
14 Power Domain Controller (PDC) that is on always-on domain. In addition to
17 well detect interrupts when the GIC is non-operational.
22 specify PDC as their interrupt controller and request the PDC port associated
28 - enum:
29 - qcom,qdu1000-pdc
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