Searched full:port (Results 1 – 25 of 1170) sorted by relevance
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| /Documentation/devicetree/bindings/media/ |
| D | renesas,isp.yaml | 44 port@0:
45 $ref: /schemas/graph.yaml#/properties/port
47 Input port node, multiple endpoints describing the connected R-Car
50 port@1:
51 $ref: /schemas/graph.yaml#/properties/port
53 Single endpoint describing the R-Car VIN connected to output port 0.
55 port@2:
56 $ref: /schemas/graph.yaml#/properties/port
58 Single endpoint describing the R-Car VIN connected to output port 1.
60 port@3:
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| D | video-mux.yaml | 15 received on the active input port is passed through to the output port. Muxes
35 '^port@':
36 $ref: /schemas/graph.yaml#/properties/port
39 - port@0
40 - port@1
41 - port@2
44 '^port@':
45 $ref: /schemas/graph.yaml#/properties/port
47 At least three port nodes containing endpoints connecting to the source
48 and sink devices according to of_graph bindings. The last port is the
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| D | cdns,csi2rx.yaml | 75 port@0:
76 $ref: /schemas/graph.yaml#/$defs/port-base
79 Input port node, single endpoint describing the CSI-2 transmitter.
102 port@1:
103 $ref: /schemas/graph.yaml#/properties/port
105 Stream 0 Output port node
107 port@2:
108 $ref: /schemas/graph.yaml#/properties/port
110 Stream 1 Output port node
112 port@3:
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| D | microchip,csi2dc.yaml | 27 accessible as a DMA slave port to a DMA controller.
29 CSI2DC supports a single 'port' node as a sink port with either Synopsys
32 CSI2DC supports one 'port' node as source port with parallel interface.
34 This port has an 'endpoint' that can be connected to a sink port of another
76 port@0:
77 $ref: /schemas/graph.yaml#/$defs/port-base
80 Input port node, single endpoint describing the input port.
105 port@1:
106 $ref: /schemas/graph.yaml#/$defs/port-base
109 Output port node, single endpoint describing the output port.
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| /Documentation/devicetree/bindings/net/ |
| D | fsl,fman-port.yaml | 4 $id: http://devicetree.org/schemas/net/fsl,fman-port.yaml#
7 title: Freescale Frame Manager Port Device
21 - fsl,fman-v2-port-oh
22 - fsl,fman-v2-port-rx
23 - fsl,fman-v2-port-tx
24 - fsl,fman-v3-port-oh
25 - fsl,fman-v3-port-rx
26 - fsl,fman-v3-port-tx
31 Specifies the hardware port id.
32 Each hardware port on the FMan has its own hardware PortID.
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| D | hisilicon-hns-nic.txt | 10 - port-id: is the index of port provided by DSAF (the accelerator). DSAF can
11 connect to 8 PHYs. Port 0 to 1 are both used for administration purpose. They
17 port-id can be 2 to 7. Here is the diagram:
23 port port
28 this switch. In this case, the port-id will be 2 only.
32 | | service| port(2)
34 port | switch |
37 external port
42 - port-idx-in-ae: is the index of port provided by AE.
44 to the CPU. The port-idx-in-ae can be 0 to 5. Here is the diagram:
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| D | hisilicon-hns-dsaf.txt | 8 "2port-64vf",
9 "6port-16rss",
10 "6port-16vf",
11 "single-port".
18 serdes-syscon in port node does not exist). It is recommended using
22 single-port mode.
26 - phy-handle: phy handle of physical port, 0 if not any phy device. It is optional
27 attribute. If port node exists, phy-handle in each port node will be used.
35 - port: subnodes of dsaf. A dsaf node may contain several port nodes(Depending
36 on mode of dsaf). Port node contain some attributes listed below:
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| /Documentation/devicetree/bindings/sound/ |
| D | qcom,wcd937x-sdw.yaml | 24 qcom,tx-port-mapping:
26 Specifies static port mapping between device and host tx ports.
27 In the order of the device port index which are adc1_port, adc23_port,
31 WCD9370 TX Port 1 (ADC1) <=> SWR2 Port 2
32 WCD9370 TX Port 2 (ADC2, 3) <=> SWR2 Port 2
33 WCD9370 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3
34 WCD9370 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4
42 qcom,rx-port-mapping:
44 Specifies static port mapping between device and host rx ports.
45 In the order of device port index which are hph_port, clsh_port,
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| /Documentation/devicetree/bindings/display/ |
| D | renesas,du.yaml | 64 The number of ports and their assignment are model-dependent. Each port
68 "^port@[0-3]$":
69 $ref: /schemas/graph.yaml#/properties/port
73 - port@0
74 - port@1
133 port@0:
135 port@1:
137 # port@2 is TCON, not supported yet
138 port@2: false
139 port@3: false
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | thine,thc63lvd1024.yaml | 32 When operating in single input mode, all pixels are received on port@0,
33 and port@1 shall not contain any endpoint. In dual input mode,
34 even-numbered pixels are received on port@0 and odd-numbered pixels on
35 port@1, and both port@0 and port@1 shall contain endpoints.
38 CMOS/TTL port and port@3 shall not contain any endpoint. In dual output
39 mode pixels are output from both CMOS/TTL ports and both port@2 and
40 port@3 shall contain endpoints.
43 port@0:
44 $ref: /schemas/graph.yaml#/properties/port
45 description: First LVDS input port
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| D | lontium,lt9211.yaml | 38 port@0:
39 $ref: /schemas/graph.yaml#/properties/port
41 Primary MIPI DSI port-1 for MIPI input or
42 LVDS port-1 for LVDS input or DPI input.
44 port@1:
45 $ref: /schemas/graph.yaml#/properties/port
47 Additional MIPI port-2 for MIPI input or LVDS port-2
49 port-1 to drive higher resolution displays
51 port@2:
52 $ref: /schemas/graph.yaml#/properties/port
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| D | cdns,mhdp8546.yaml | 64 port@0:
65 $ref: /schemas/graph.yaml#/properties/port
67 First input port representing the DP bridge input.
69 port@1:
70 $ref: /schemas/graph.yaml#/properties/port
72 Second input port representing the DP bridge input.
74 port@2:
75 $ref: /schemas/graph.yaml#/properties/port
77 Third input port representing the DP bridge input.
79 port@3:
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| D | lontium,lt9611.yaml | 7 title: Lontium LT9611(UXC) 2 Port MIPI to HDMI Bridge
44 port@0:
45 $ref: /schemas/graph.yaml#/properties/port
47 Primary MIPI port-1 for MIPI input
49 port@1:
50 $ref: /schemas/graph.yaml#/properties/port
52 Additional MIPI port-2 for MIPI input, used in combination
53 with primary MIPI port-1 to drive higher resolution displays
55 port@2:
56 $ref: /schemas/graph.yaml#/properties/port
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| D | ti,sn65dsi83.yaml | 42 port@0:
43 $ref: /schemas/graph.yaml#/$defs/port-base
45 description: Video port for MIPI DSI Channel-A input
62 port@1:
63 $ref: /schemas/graph.yaml#/$defs/port-base
65 description: Video port for MIPI DSI Channel-B input
82 port@2:
83 $ref: /schemas/graph.yaml#/properties/port
84 description: Video port for LVDS Channel-A output (panel or bridge).
86 port@3:
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| D | fsl,ldb.yaml | 42 port@0:
43 $ref: /schemas/graph.yaml#/properties/port
44 description: Video port for DPI input.
46 port@1:
47 $ref: /schemas/graph.yaml#/properties/port
48 description: Video port for LVDS Channel-A output (panel or bridge).
50 port@2:
51 $ref: /schemas/graph.yaml#/properties/port
52 description: Video port for LVDS Channel-B output (panel or bridge).
55 - port@0
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | ti,ds90ub960.yaml | 124 port@0:
125 $ref: /schemas/graph.yaml#/$defs/port-base
134 Endpoint for FPD-Link port. If the RX mode for this port is RAW,
137 port@1:
138 $ref: /schemas/graph.yaml#/$defs/port-base
147 Endpoint for FPD-Link port. If the RX mode for this port is RAW,
150 port@2:
151 $ref: /schemas/graph.yaml#/$defs/port-base
160 Endpoint for FPD-Link port. If the RX mode for this port is RAW,
163 port@3:
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| D | adv7180.yaml | 46 port:
47 $ref: /schemas/graph.yaml#/$defs/port-base
79 - port
91 port@3:
92 $ref: /schemas/graph.yaml#/properties/port
93 description: Output port
96 "^port@[0-2]$":
97 $ref: /schemas/graph.yaml#/properties/port
98 description: Input port
101 - port@3
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| D | st,st-mipid02.yaml | 15 active at a time. Active port input stream will be de-serialized
16 and its content outputted through PARALLEL output port.
17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
18 second input port is a single lane 800Mbps. Both ports support clock
19 and data lane polarity swap. First port also supports data lane swap.
20 PARALLEL output port has a maximum width of 12 bits.
53 port@0:
54 $ref: /schemas/graph.yaml#/$defs/port-base
56 description: CSI-2 first input port
79 port@1:
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| /Documentation/devicetree/bindings/usb/ |
| D | realtek,rts5411.yaml | 43 port@1:
44 $ref: /schemas/graph.yaml#/properties/port
46 1st downstream facing USB port
48 port@2:
49 $ref: /schemas/graph.yaml#/properties/port
51 2nd downstream facing USB port
53 port@3:
54 $ref: /schemas/graph.yaml#/properties/port
56 3rd downstream facing USB port
58 port@4:
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| D | onnn,nb7vpq904m.yaml | 30 port@0:
31 $ref: /schemas/graph.yaml#/properties/port
34 port@1:
35 $ref: /schemas/graph.yaml#/$defs/port-base
56 The position determines the physical port of the redriver, in the
66 - Port A to RX2 lane
67 - Port B to TX2 lane
68 - Port C to TX1 lane
69 - Port D to RX1 lane
77 - Port A to RX1 lane
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| /Documentation/networking/devlink/ |
| D | devlink-port.rst | 6 Devlink Port
9 ``devlink-port`` is a port that exists on the device. It has a logically
10 separate ingress/egress point of the device. A devlink port can be any one
11 of many flavours. A devlink port flavour along with port attributes
12 describe what a port represents.
14 A device driver that intends to publish a devlink port sets the
15 devlink port attributes and registers the devlink port.
17 Devlink port flavours are described below.
19 .. list-table:: List of devlink port flavours
25 - Any kind of physical port. This can be an eswitch physical port or any
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| /Documentation/PCI/ |
| D | pciebus-howto.rst | 5 The PCI Express Port Bus Driver Guide HOWTO
14 This guide describes the basics of the PCI Express Port Bus driver
16 register/unregister with the PCI Express Port Bus Driver.
19 What is the PCI Express Port Bus Driver
22 A PCI Express Port is a logical PCI-PCI Bridge structure. There
23 are two types of PCI Express Port: the Root Port and the Switch
24 Port. The Root Port originates a PCI Express link from a PCI Express
25 Root Complex and the Switch Port connects PCI Express links to
26 internal logical PCI buses. The Switch Port, which has its secondary
28 switch's Upstream Port. The switch's Downstream Port is bridging from
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | mediatek,mt7530.yaml | 26 CPU port and 4 user ports connected to the built-in Gigabit Ethernet PHYs.
34 Port 5 on MT7530 supports various configurations:
36 - Port 5 can be used as a CPU port.
39 the gmac of the SoC which is wired to port 5 can connect to the PHY.
40 This is usually used for connecting the wan port directly to the CPU to
55 gmac1 of the SoC, port 5 must not be enabled.
63 - Port 5 can be wired to an external phy. Port 5 becomes a DSA user port.
115 port 0 LED 0..2 as GPIO 0..2
116 port 1 LED 0..2 as GPIO 3..5
117 port 2 LED 0..2 as GPIO 6..8
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| /Documentation/ABI/testing/ |
| D | sysfs-class-typec | 1 USB Type-C port devices (eg. /sys/class/typec/port0/)
3 What: /sys/class/typec/<port>/data_role
8 requesting data role swapping on the port. Swapping is supported
13 KOBJ_CHANGE on the port. The current role is show in brackets,
14 for example "[host] device" when DRP port is in host mode.
18 What: /sys/class/typec/<port>/power_role
23 power role swap on the port. Swapping is supported as
33 What: /sys/class/typec/<port>/port_type
37 Indicates the type of the port. This attribute can be used for
38 requesting a change in the port type. Port type change is
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| /Documentation/devicetree/bindings/display/imx/ |
| D | fsl,imx6-hdmi.yaml | 44 HDMI multiplexer. Each port shall have a single endpoint.
47 port@0:
48 $ref: /schemas/graph.yaml#/properties/port
51 port@1:
52 $ref: /schemas/graph.yaml#/properties/port
55 port@2:
56 $ref: /schemas/graph.yaml#/properties/port
59 port@3:
60 $ref: /schemas/graph.yaml#/properties/port
65 - port@0
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