Searched full:ppi (Results 1 – 14 of 14) sorted by relevance
| /Documentation/ABI/testing/ |
| D | sysfs-driver-ppi | 1 What: /sys/class/tpm/tpmX/ppi/
6 This folder includes the attributes related with PPI (Physical
9 'find /sys/ -name 'pcrs''. For the detail information of PPI,
10 please refer to the PPI specification from
14 In Linux 4.2 ppi was moved to the character device directory.
15 A symlink from tpmX/device/ppi to tpmX/ppi to provide backwards
18 What: /sys/class/tpm/tpmX/ppi/version
22 This attribute shows the version of the PPI supported by the
26 What: /sys/class/tpm/tpmX/ppi/request
36 What: /sys/class/tpm/tpmX/ppi/response
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic-v3.yaml | 14 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
43 If the system requires describing PPI affinity, then the value must
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
48 Extended PPI range. Other values are reserved for future use.
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
53 Extended PPI interrupts are in the range [0-127].
61 interrupt is affine to. The interrupt must be a PPI, and the node
62 pointed must be a subnode of the "ppi-partitions" subnode. For
63 interrupt types other than PPI or PPIs that are not partitioned,
64 this cell must be zero. See the "ppi-partitions" node description
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| D | arm,gic.yaml | 14 interrupts (PPI), shared processor interrupts (SPI) and software
74 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
78 SPI interrupts are in the range [0-987]. PPI interrupts are in the
87 bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
89 the interrupt is wired to that CPU. Only valid for PPI interrupts.
90 Also note that the configurability of PPI interrupts is IMPLEMENTATION
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| /Documentation/devicetree/bindings/perf/ |
| D | spe-pmu.yaml | 23 The PPI to signal SPE events. For heterogeneous systems where SPE is only
25 for details on describing a PPI partition.
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| /Documentation/devicetree/bindings/arm/ |
| D | pmu.yaml | 80 description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
91 When using a PPI, specifies a list of phandles to CPU
93 a PMU of this type signalling the PPI listed in the
95 by the PPI interrupt specifier itself (in which case
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| D | arm,trace-buffer-extension.yaml | 30 Exactly 1 PPI must be listed. For heterogeneous systems where
32 the arm,gic-v3 binding for details on describing a PPI partition.
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | renesas,dsi.yaml | 38 - description: DSI D-PHY PPI interrupt
48 - const: ppi
149 "ferr", "ppi", "debug";
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| /Documentation/virt/kvm/devices/ |
| D | vcpu.rst | 38 number for this vcpu. This interrupt could be a PPI or SPI, but the interrupt
39 type must be same for each vcpu. As a PPI, the interrupt number is the same for
159 in-kernel virtual GIC. These must be a PPI (16 <= intid < 32). Setting the
167 Setting the same PPI for different timers will prevent the VCPUs from running.
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| D | arm-vgic.rst | 131 A value describing the number of interrupts (SGI, PPI and SPI) for
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| D | arm-vgic-v3.rst | 220 A value describing the number of interrupts (SGI, PPI and SPI) for
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| /Documentation/virt/geniezone/ |
| D | introduction.rst | 85 we intend to support all SPI, PPI, and SGI. When it comes to virtual
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| /Documentation/driver-api/media/drivers/ |
| D | ipu6.rst | 171 see the PPI mmapping in ``ipu6-isys-mcd-phy.c`` for more information. On Jasper
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| /Documentation/virt/hyperv/ |
| D | vmbus.rst | 177 an 8-bit x86/x64 interrupt vector, or an arm64 PPI INTID). Because
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| /Documentation/virt/kvm/ |
| D | api.rst | 900 in-kernel GIC: PPI, irq_id between 16 and 31 (incl.)
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