Searched full:pr (Results 1 – 19 of 19) sorted by relevance
| /Documentation/devicetree/bindings/fpga/ |
| D | xlnx,pr-decoupler.yaml | 4 $id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
16 The Xilinx LogiCORE Partial Reconfig(PR) Decoupler manages one or more
22 is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
35 - const: xlnx,pr-decoupler-1.00
36 - const: xlnx,pr-decoupler
62 compatible = "xlnx,pr-decoupler-1.00", "xlnx,pr-decoupler";
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| D | altera-pr-ip.txt | 4 - compatible : should contain "altr,a10-pr-ip"
10 compatible = "altr,a10-pr-ip";
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| D | fpga-region.yaml | 41 Partial Reconfiguration (PR)
44 * Not all FPGA's support PR.
131 FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA
157 For partial reconfiguration (PR), each PR region will have an FPGA Region.
169 region is getting reconfigured (see Figure 1 above). During PR, the FPGA's
170 hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges
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| /Documentation/block/ |
| D | index.rst | 20 pr
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| /Documentation/ABI/testing/ |
| D | sysfs-platform-dfl-port | 13 Description: Read-only. User can program different PR bitstreams to FPGA
15 returns uuid which could be used to identify which PR bitstream
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| /Documentation/devicetree/bindings/soc/microchip/ |
| D | microchip,mpfs-sys-controller.yaml | 17 https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html
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| /Documentation/devicetree/bindings/clock/ |
| D | microchip,mpfs-ccc.yaml | 16 https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
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| /Documentation/fpga/ |
| D | dfl.rst | 282 never cause any system level issue, only functional failure (e.g. DMA or PR
291 afu_id indicates which PR bitstream is programmed to this AFU.
343 bridges and FPGA regions during PR sub feature initialization. Once
346 reconfiguration of the PR bitstream to the given port.
363 reconfiguration of a PR bitstream file. The PR bitstream file must have been
367 comparing the compatibility ID noted in the header of PR bitstream file against
464 Note that an FME can't be assigned to a VF, thus PR and other management
621 FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
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| /Documentation/devicetree/bindings/powerpc/ |
| D | ibm,powerpc-cpu-features.txt | 99 bit 0 - PR (problem state / user mode)
179 This property may exist when the usable-privilege property value has PR bit set.
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| /Documentation/crypto/ |
| D | api-samples.rst | 162 char *drbg = "drbg_nopr_sha256"; /* Hash DRBG with SHA-256, no PR */
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| /Documentation/translations/zh_CN/core-api/ |
| D | printk-formats.rst | 195 %pr [mem 0x60000000-0x6fffffff flags 0x2200] or
197 %pR [mem 0x60000000-0x6fffffff pref] or
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| /Documentation/driver-api/md/ |
| D | md-cluster.rst | 184 receiver tries to get PR on "message"
202 receiver upconvert to PR on "message"
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| /Documentation/virt/kvm/ |
| D | ppc-pv.rst | 8 space code in PR=1 which is user space. This way we trap all privileged
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| /Documentation/core-api/ |
| D | printk-formats.rst | 211 %pr [mem 0x60000000-0x6fffffff flags 0x2200] or
213 %pR [mem 0x60000000-0x6fffffff pref] or
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| /Documentation/arch/powerpc/ |
| D | ultravisor.rst | 69 MSR(S, HV, PR). In each of the tables below the modes are listed
76 | S | HV| PR|Privilege |
90 | S | HV| PR|Privilege |
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| /Documentation/admin-guide/thermal/ |
| D | intel_powerclamp.rst | 311 PID USER PR NI VIRT RES SHR S %CPU %MEM TIME+ COMMAND
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| /Documentation/filesystems/ |
| D | gfs2-glocks.rst | 33 SH PR (Protected read)
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| /Documentation/networking/ |
| D | arcnet-hardware.rst | 233 RP-------P--------P--------H-----P------P-----PR
235 RP-----H--------P--------H-----P------PR
237 PR PR
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| /Documentation/admin-guide/ |
| D | kernel-parameters.txt | 6051 sched_thermal_decay_shift thermal pressure decay pr
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