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/Documentation/devicetree/bindings/firmware/
Dintel,ixp4xx-network-processing-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx Network Processing Engine
11 - Linus Walleij <linus.walleij@linaro.org>
14 On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
24 - items:
25 - const: intel,ixp4xx-network-processing-engine
29 - description: NPE0 (NPE-A) register range
[all …]
/Documentation/netlabel/
Dcipso_ipv4.rst2 NetLabel CIPSO/IPv4 Protocol Engine
12 The NetLabel CIPSO/IPv4 protocol engine is based on the IETF Commercial
15 (draft-ietf-cipso-ipsecurity-01.txt). While the IETF draft never made
16 it to an RFC standard it has become a de-facto standard for labeled
19 Outbound Packet Processing
22 The CIPSO/IPv4 protocol engine applies the CIPSO IP option to packets by
31 Inbound Packet Processing
34 The CIPSO/IPv4 protocol engine validates every CIPSO IP option it finds at the
44 The CIPSO/IPv4 protocol engine contains a mechanism to translate CIPSO security
56 CIPSO/IPv4 protocol engine supports this caching mechanism.
/Documentation/devicetree/bindings/media/
Dti,vpe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments DRA7x Video Processing Engine (VPE)
10 - Benoit Parrot <bparrot@ti.com>
12 description: |-
13 The Video Processing Engine (VPE) is a key component for image post
14 processing applications. VPE consist of a single memory to memory
20 const: ti,dra7-vpe
24 - description: The VPE main register region
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Dnxp,dw100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xavier Roumegue <xavier.roumegue@oss.nxp.com>
12 description: |-
13 The Dewarp Engine provides high-performance dewarp processing for the
15 and wide angle lenses. It is implemented with a line/tile-cache based
17 processing, it successfully generates a corrected output image.
18 The engine can be used to perform scaling, cropping and pixel format
24 - nxp,imx8mp-dw100
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Dnvidia,tegra-vde.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Video Decoder Engine
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
[all …]
Drenesas,vsp1.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas VSP Video Processing Engine
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The VSP is a video processing engine that supports up-/down-scaling, alpha
14 blending, color space conversion and various other image processing features.
15 It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs.
20 - enum:
21 - renesas,r9a07g044-vsp2 # RZ/G2L
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Dfsl,imx6ull-pxp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/fsl,imx6ull-pxp.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Philipp Zabel <p.zabel@pengutronix.de>
12 - Michael Tretter <m.tretter@pengutronix.de>
15 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
23 - enum:
24 - fsl,imx6ul-pxp
25 - fsl,imx6ull-pxp
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Dnxp,imx8-isi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8-isi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The Image Sensing Interface (ISI) combines image processing pipelines with
16 number and nature is SoC-dependent. They cover both capture interfaces (MIPI
17 CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
22 - fsl,imx8mn-isi
23 - fsl,imx8mp-isi
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/Documentation/devicetree/bindings/sound/
Dnvidia,tegra210-ope.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ope.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Output Processing Engine (OPE) is one of the AHUB client. It has
12 sub blocks for data processing.
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Mohan Kumar <mkumard@nvidia.com>
17 - Sameer Pujar <spujar@nvidia.com>
20 - $ref: dai-common.yaml#
[all …]
Dnvidia,tegra210-mbdrc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-mbdrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 Processing Engine (OPE) which interfaces with Audio Hub (AHUB) via
16 - Jon Hunter <jonathanh@nvidia.com>
17 - Mohan Kumar <mkumard@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
23 - const: nvidia,tegra210-mbdrc
24 - items:
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Dnvidia,tegra210-peq.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-peq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 PEQ sits inside Output Processing Engine (OPE) which interfaces
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Mohan Kumar <mkumard@nvidia.com>
19 - Sameer Pujar <spujar@nvidia.com>
24 - const: nvidia,tegra210-peq
25 - items:
[all …]
Dnvidia,tegra210-ahub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 for audio pre-processing, post-processing and a programmable full
14 engine through ADMAIF.
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^ahub@[0-9a-f]*$"
26 - enum:
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/Documentation/crypto/
Dcrypto_engine.rst1 .. SPDX-License-Identifier: GPL-2.0
3 Crypto Engine
7 --------
8 The crypto engine (CE) API is a crypto queue manager.
11 -----------
18 struct crypto_engine engine;
22 The crypto engine only manages asynchronous requests in the form of
25 using container_of. In addition, the engine knows nothing about your
26 structure "``struct your_tfm_ctx``". The engine assumes (requires) the placement
30 -------------------
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/Documentation/devicetree/bindings/crypto/
Dintel,ixp4xx-crypto.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx cryptographic engine
11 - Linus Walleij <linus.walleij@linaro.org>
14 The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
15 (Network Processing Engine). Since it is not a device on its own
21 const: intel,ixp4xx-crypto
23 intel,npe-handle:
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/Documentation/admin-guide/media/
Dplatform-cardlist.rst1 .. SPDX-License-Identifier: GPL-2.0
17 am437x-vpfe TI AM437x VPFE
18 aspeed-video Aspeed AST2400 and AST2500
19 atmel-isc ATMEL Image Sensor Controller (ISC)
20 atmel-isi ATMEL Image Sensor Interface (ISI)
24 cdns-csi2rx Cadence MIPI-CSI2 RX Controller
25 cdns-csi2tx Cadence MIPI-CSI2 TX Controller
26 coda-vpu Chips&Media Coda multi-standard codec IP
29 exynos-fimc-is EXYNOS4x12 FIMC-IS (Imaging Subsystem)
30 exynos-fimc-lite EXYNOS FIMC-LITE camera interface
[all …]
/Documentation/devicetree/bindings/net/
Dintel,ixp4xx-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-ethernet.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Linus Walleij <linus.walleij@linaro.org>
18 Processing Engine) and the IXP4xx Queue Manager to process
24 const: intel,ixp4xx-ethernet
30 queue-rx:
31 $ref: /schemas/types.yaml#/definitions/phandle-array
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Dintel,ixp4xx-hss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Linus Walleij <linus.walleij@linaro.org>
15 Processing Engine) and the IXP4xx Queue Manager to process
20 const: intel,ixp4xx-hss
26 intel,npe-handle:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
30 - description: phandle to the NPE this HSS instance is using
[all …]
/Documentation/gpu/amdgpu/display/
Ddc-glossary.rst7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
16 Accelerated Processing Unit
19 Application-Specific Integrated Circuit
25 Azalia (HD audio DMA engine)
36 * SOCCLK: GPU Engine Clock
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
68 Display Controller Engine
108 Display Micro-Controller Unit
111 Display Micro-Controller Unit, version B
225 Transition-Minimized Differential Signaling
/Documentation/devicetree/bindings/misc/
Dxlnx,sd-fec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cvetic, Dragan <dragan.cvetic@amd.com>
11 - Erim, Salih <salih.erim@amd.com>
14 The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
15 which provides high-throughput LDPC and Turbo Code implementations.
17 customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
18 principally covers codes used by LTE. The FEC Engine offers significant
[all …]
/Documentation/devicetree/bindings/bus/
Dnvidia,tegra210-aconnect.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/nvidia,tegra210-aconnect.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 components inside the Audio Processing Engine (APE). All CPU accesses to
13 devices accessed via the ACONNECT are described by child-nodes.
16 - Jon Hunter <jonathanh@nvidia.com>
21 - const: nvidia,tegra210-aconnect
22 - items:
23 - enum:
[all …]
/Documentation/devicetree/bindings/display/hisilicon/
Dhisi-ade.txt1 Device-Tree bindings for hisilicon ADE display controller driver
3 ADE (Advanced Display Engine) is the display controller which grab image
4 data from memory, do composition, do post image processing, generate RGB
8 - compatible: value should be "hisilicon,hi6220-ade".
9 - reg: physical base address and length of the ADE controller's registers.
10 - hisilicon,noc-syscon: ADE NOC QoS syscon.
11 - resets: The ADE reset controller node.
12 - interrupt: the ldi vblank interrupt number used.
13 - clocks: a list of phandle + clock-specifier pairs, one for each entry
14 in clock-names.
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/Documentation/userspace-api/media/v4l/
Ddev-subdev.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
6 Sub-device Interface
13 components as software blocks called sub-devices.
15 V4L2 sub-devices are usually kernel-only objects. If the V4L2 driver
17 media entities. Applications will be able to enumerate the sub-devices
21 In addition to make sub-devices discoverable, drivers can also choose to
23 sub-device driver and the V4L2 device driver support this, sub-devices
26 - query, read and write sub-devices controls
28 - subscribe and unsubscribe to events and retrieve them
30 - negotiate image formats on individual pads
[all …]
/Documentation/devicetree/bindings/iio/imu/
Dinvensense,icm42600.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: InvenSense ICM-426xx Inertial Measurement Unit
10 - Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>
13 6-axis MotionTracking device that combines a 3-axis gyroscope and a 3-axis
18 ultra-low-power wake-on-motion support to minimize system power consumption.
20 Other industry-leading features include InvenSense on-chip APEX Motion
21 Processing engine for gesture recognition, activity classification, and
25 https://invensense.tdk.com/wp-content/uploads/2020/03/DS-000292-ICM-42605-v1.4.pdf
[all …]
/Documentation/devicetree/bindings/dma/
Dnvidia,tegra210-adma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/nvidia,tegra210-adma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 between system memory and the Audio Processing Engine (APE).
14 - Jon Hunter <jonathanh@nvidia.com>
17 - $ref: dma-controller.yaml#
22 - enum:
23 - nvidia,tegra210-adma
24 - nvidia,tegra186-adma
[all …]
/Documentation/driver-api/
Dlibata.rst12 transports for ATA and ATAPI devices, and SCSI<->ATA translation for ATA
16 internals, and a couple sample ATA low-level drivers.
22 is defined for every low-level libata
23 hardware driver, and it controls how the low-level driver interfaces
26 FIS-based drivers will hook into the system with ``->qc_prep()`` and
27 ``->qc_issue()`` high-level hooks. Hardware which behaves in a manner
33 ----------------------------------------------------------
35 Post-IDENTIFY device configuration
44 Typically used to apply device-specific fixups prior to issue of SET
45 FEATURES - XFER MODE, and prior to operation.
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