Searched +full:processor +full:- +full:a +full:- +full:side (Results 1 – 25 of 53) sorted by relevance
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | fsl,mu-msi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
16 for one processor (A side) to signal the other processor (B side) using
20 different clocks (from each side of the different peripheral buses).
21 Therefore, the MU must synchronize the accesses from one side to the
23 registers (Processor A-side, Processor B-side).
28 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
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| /Documentation/devicetree/bindings/mailbox/ |
| D | fsl,mu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
16 for one processor to signal the other processor using interrupts.
19 different clocks (from each side of the different peripheral buses).
20 Therefore, the MU must synchronize the accesses from one side to the
22 registers (Processor A-facing, Processor B-facing).
27 - const: fsl,imx6sx-mu
28 - const: fsl,imx7ulp-mu
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,smp2p.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
16 of a single 32-bit value between two processors. Each value has a single
17 writer (the local side) and a single reader (the remote side). Values are
18 uniquely identified in the system by the directed edge (local processor ID to
19 remote processor ID) and a string identifier.
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| /Documentation/admin-guide/hw-vuln/ |
| D | gather_data_sampling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 GDS - Gather Data Sampling
6 Gather Data Sampling is a hardware vulnerability which allows unprivileged
10 -------
11 When a gather instruction performs loads from memory, different data elements
12 are merged into the destination vector register. However, when a gather
13 instruction that is transiently executed encounters a fault, stale data from
15 destination vector register instead. This will allow a malicious attacker to
16 infer stale data using typical side channel techniques like cache timing
17 attacks. GDS is a purely sampling-based attack.
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| D | spectre.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 Spectre Side Channels
6 Spectre is a class of side channel attacks that exploit branch prediction
8 bypassing access controls. Speculative execution side channel exploits
14 -------------------
16 Speculative execution side channel methods affect a wide range of modern
22 - Intel Core, Atom, Pentium, and Xeon processors
24 - AMD Phenom, EPYC, and Zen processors
26 - IBM POWER and zSeries processors
28 - Higher end ARM processors
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| D | mds.rst | 1 MDS - Microarchitectural Data Sampling
4 Microarchitectural Data Sampling is a hardware vulnerability which allows
9 -------------------
11 This vulnerability affects a wide range of Intel processors. The
14 - Processors from AMD, Centaur and other non Intel vendors
16 - Older processor models, where the CPU family is < 6
18 - Some Atoms (Bonnell, Saltwell, Goldmont, GoldmontPlus)
20 - Intel processors which have the ARCH_CAP_MDS_NO bit set in the
23 Whether a processor is affected or not can be read out from the MDS
27 is identical for all of them so the kernel treats them as a single
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| D | tsx_async_abort.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 TAA - TSX Asynchronous Abort
6 TAA is a hardware vulnerability that allows unprivileged speculative access to
11 -------------------
19 Whether a processor is affected or not can be read out from the TAA
23 ------------
28 CVE-2019-11135 TAA TSX Asynchronous Abort (TAA) condition on some
31 information disclosure via a side channel with
36 -------
43 hardware transactional memory support to improve performance of multi-threaded
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| D | srso.rst | 1 .. SPDX-License-Identifier: GPL-2.0
6 This is a mitigation for the speculative return stack overflow (SRSO)
8 known scenario of poisoning CPU functional units - the Branch Target
9 Buffer (BTB) and Return Address Predictor (RAP) in this case - and then
13 AMD CPUs predict RET instructions using a Return Address Predictor (aka
14 Return Address Stack/Return Stack Buffer). In some cases, a non-architectural
15 CALL instruction (i.e., an instruction predicted to be a CALL but is
16 not actually a CALL) can create an entry in the RAP which may be used
17 to predict the target of a subsequent RET instruction.
20 but the concern is that an attacker can mis-train the CPU BTB to predict
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,coresight-dummy-source.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-dummy-source.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 specification and can be connected in various topologies to suit a particular
19 there would be Coresight source trace components on sub-processor which
20 are connected to AP processor via debug bus. For these devices, a dummy driver
27 side for dummy source component.
30 - Mike Leach <mike.leach@linaro.org>
31 - Suzuki K Poulose <suzuki.poulose@arm.com>
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| D | arm,coresight-dummy-sink.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-dummy-sink.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 specification and can be connected in various topologies to suit a particular
19 Qualcomm platforms. It is a mini-USB hub implemented to support the USB-based
20 debug and trace capabilities. For this device, a dummy driver is needed to
21 register it as Coresight sink device in kernel side, so that path can be
23 coresight link of AP processor. It provides Coresight API for operations on
28 side for dummy sink component.
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | st,stm32-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/st,stm32-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 remote processor controller
14 - Fabien Dessenne <fabien.dessenne@foss.st.com>
15 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
19 const: st,stm32mp1-m4
24 processor.
31 reset-names:
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| D | qcom,sc7280-wpss-pil.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-wpss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 This document defines the binding for a component that loads and boots firmware
19 - qcom,sc7280-wpss-pil
28 - description: Watchdog interrupt
29 - description: Fatal interrupt
30 - description: Ready interrupt
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| /Documentation/hwmon/ |
| D | lm70.rst | 35 -----------
40 The LM70 temperature sensor chip supports a single temperature sensor.
41 It communicates with a host processor (or microcontroller) via an
46 comprise the MOSI/MISO loop. At the end of the transfer, the 11-bit 2's
48 driver for interpretation. This driver makes use of the kernel's in-core
51 As a real (in-tree) example of this "SPI protocol driver" interfacing
52 with a "SPI master controller driver", see drivers/spi/spi_lm70llp.c
56 13-bit temperature data (0.0625 degrees celsius resolution).
60 The TMP125 is less accurate and provides 10-bit temperature data
63 The LM71 is also very similar; main difference is 14-bit temperature
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | cpm.txt | 1 * Freescale Communications Processor Module
10 - compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
11 - reg : A 48-byte region beginning with CPCR.
15 #address-cells = <1>;
16 #size-cells = <1>;
17 #interrupt-cells = <2>;
18 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
24 - fsl,cpm-command : This value is ORed with the opcode and command flag
25 to specify the device on which a CPM command operates.
27 - fsl,cpm-brg : Indicates which baud rate generator the device
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| /Documentation/input/devices/ |
| D | walkera0701.rst | 2 Walkera WK-0701 transmitter
5 Walkera WK-0701 transmitter is supplied with a ready to fly Walkera
10 http://zub.fei.tuke.sk/walkera-wk0701/
13 cg-clone http://zub.fei.tuke.sk/GIT/walkera0701-joystick
19 At back side of transmitter S-video connector can be found. Modulation
20 pulses from processor to HF part can be found at pin 2 of this connector,
26 Walkera WK-0701 TX S-VIDEO connector::
28 (back side of TX)
29 __ __ S-video: canon25
35 ------- 3 __________________________________|________________ 25 GND
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| /Documentation/hid/ |
| D | intel-ish-hid.rst | 5 A sensor hub enables the ability to offload sensor polling and algorithm
6 processing to a dedicated low power co-processor. This allows the core
7 processor to go into low power modes more often, resulting in increased
11 Sensor usage tables. These may be found in tablets, 2-in-1 convertible laptops
14 Intel® introduced integrated sensor hubs as a part of the SoC starting from
24 Using a analogy with a usbhid implementation, the ISH follows a similar model
25 for a very high speed communication::
27 ----------------- ----------------------
28 | USB HID | --> | ISH HID |
29 ----------------- ----------------------
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| /Documentation/process/ |
| D | volatile-considered-harmful.rst | 5 ------------------------------------------------
8 changed outside of the current thread of execution; as a result, they are
11 as a sort of easy atomic variable, which they are not. The use of volatile in
17 unwanted concurrent access, which is very much a different task. The
19 all optimization-related problems in a more efficient way.
25 almost certainly a bug in the code somewhere. In properly-written kernel
28 Consider a typical block of kernel code::
38 primitives act as memory barriers - they are explicitly written to do so -
41 spin_lock() call, since it acts as a memory barrier, will force it to
50 unnecessary - and potentially harmful.
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| D | stable-api-nonsense.rst | 8 Greg Kroah-Hartman <greg@kroah.com>
10 This is being written to try to explain why Linux **does not have a binary
11 kernel interface, nor does it have a stable kernel interface**.
20 will not break. I have old programs that were built on a pre 0.9something
27 -----------------
28 You think you want a stable kernel interface, but you really do not, and
29 you don't even know it. What you want is a stable running driver, and
32 tree, all of which has made Linux into such a strong, stable, and mature
38 -----
40 It's only the odd person who wants to write a kernel driver that needs
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| /Documentation/core-api/ |
| D | cachetlb.rst | 9 describes its intended purpose, and what side effect is expected
12 The side effects described below are stated for a uniprocessor
13 implementation, and what is to happen on that single processor. The
14 SMP cases are a simple extension, in that you just extend the
15 definition such that the side effect for a particular interface occurs
19 if it can be proven that a user address space has never executed
20 on a cpu (see mm_cpumask()), one need not perform a flush
25 virtual-->physical address translations obtained from the software
56 Here we are flushing a specific range of (user) virtual
59 modifications for the address space 'vma->vm_mm' in the range
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| /Documentation/arch/arm/ |
| D | cluster-pm-race-avoidance.rst | 2 Cluster-wide Power-up/power-down race avoidance algorithm
10 needed. "Basic model" explains general concepts using a simplified view
16 ---------
18 In a system containing multiple CPUs, it is desirable to have the
22 In a system containing multiple clusters of CPUs, it is also desirable
25 Turning entire clusters off and on is a risky business, because it
26 involves performing potentially destructive operations affecting a group
29 cluster-level operations are only performed when it is truly safe to do
34 are not immediately enabled when a cluster powers up. Since enabling or
35 disabling those mechanisms may itself be a non-atomic operation (such as
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| /Documentation/driver-api/ |
| D | xillybus.rst | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
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| /Documentation/arch/s390/ |
| D | vfio-ccw.rst | 2 vfio-ccw: the basic infrastructure
6 ------------
9 Linux/s390. Motivation for vfio-ccw is to passthrough subchannels to a
12 Different than other hardware architectures, s390 has defined a unified
16 - Channel programs run asynchronously on a separate (co)processor.
17 - The channel subsystem will access any memory designated by the caller
21 with a mediated device (mdev) implementation. The vfio mdev will be
31 - A good start to know Channel I/O in general:
33 - s390 architecture:
34 s390 Principles of Operation manual (IBM Form. No. SA22-7832)
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| /Documentation/devicetree/bindings/net/ |
| D | qcom,ipa.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alex Elder <elder@kernel.org>
15 the main processor.
18 including the Application Processor (AP) and the modem. The IPA presents
19 a Generic Software Interface (GSI) to each execution environment.
21 and has a distinct interrupt and a separately-defined address space.
28 - |
29 -------- ---------
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| /Documentation/arch/powerpc/ |
| D | syscall64-abi.rst | 2 Power Architecture 64-bit Linux system call ABI
9 ----------
17 syscall calling sequence\ [1]_ matches the Power Architecture 64-bit ELF ABI
21 .. [1] Some syscalls (typically low-level management functions) may have
25 ----------
28 There is a maximum of 6 integer parameters to a syscall, passed in r3-r8.
31 ------------
32 - For the sc instruction, both a value and an error condition are returned.
38 - For the scv 0 instruction, the return value indicates failure if it is
39 -4095..-1 (i.e., it is >= -MAX_ERRNO (-4095) as an unsigned comparison),
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| /Documentation/arch/arm64/ |
| D | acpi_object_usage.rst | 8 If a section number is used, it refers to a section number in the ACPI
16 - Required: DSDT, FADT, GTDT, MADT, MCFG, RSDP, SPCR, XSDT
18 - Recommended: BERT, EINJ, ERST, HEST, PCCT, SSDT
20 - Optional: AGDI, BGRT, CEDT, CPEP, CSRT, DBG2, DRTM, ECDT, FACS, FPDT,
24 - Not supported: AEST, APMT, BOOT, DBGP, DMAR, ETDT, HPET, IVRS, LPIT,
41 This table describes a non-maskable event, that is used by the platform
42 firmware, to request the OS to generate a diagnostic dump and reset the device.
68 Optional, not currently supported, with no real use-case for an
83 time as ARM-compatible hardware is available, and the specification
109 A DSDT is required; see also SSDT.
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