Searched full:processors (Results 1 – 25 of 199) sorted by relevance
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| /Documentation/arch/arm/ |
| D | marvell.rst | 44 …s://web.archive.org/web/20111027032509/http://www.marvell.com/embedded-processors/armada-300/asset…
47 …s://web.archive.org/web/20111027032509/http://www.marvell.com/embedded-processors/armada-300/asset…
50 …s://web.archive.org/web/20130730072715/http://www.marvell.com/embedded-processors/kirkwood/assets/…
51 …s://web.archive.org/web/20121021182835/http://www.marvell.com/embedded-processors/kirkwood/assets/…
52 …s://web.archive.org/web/20130730091033/http://www.marvell.com/embedded-processors/kirkwood/assets/…
55 …s://web.archive.org/web/20131113121446/http://www.marvell.com/embedded-processors/kirkwood/assets/…
56 …s://web.archive.org/web/20121021182835/http://www.marvell.com/embedded-processors/kirkwood/assets/…
57 …s://web.archive.org/web/20130730091033/http://www.marvell.com/embedded-processors/kirkwood/assets/…
61 …s://web.archive.org/web/20120616201621/http://www.marvell.com/embedded-processors/kirkwood/assets/…
62 …s://web.archive.org/web/20130730091654/http://www.marvell.com/embedded-processors/kirkwood/assets/…
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| /Documentation/hwmon/ |
| D | k10temp.rst | 6 * AMD Family 10h processors:
16 * AMD Family 11h processors:
20 * AMD Family 12h processors: "Llano" (E2/A4/A6/A8-Series)
22 * AMD Family 14h processors: "Brazos" (C/E/G/Z-Series)
24 * AMD Family 15h processors: "Bulldozer" (FX-Series), "Trinity", "Kaveri",
27 * AMD Family 16h processors: "Kabini", "Mullins"
29 * AMD Family 17h processors: "Zen", "Zen 2"
31 * AMD Family 18h processors: "Hygon Dhyana"
33 * AMD Family 19h processors: "Zen 3"
41 BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors:
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| D | coretemp.rst | 70 22nm Core i5/i7 Processors
81 32nm Core i3/i5/i7 Processors
88 32nm Core i7 Extreme Processors
91 32nm Celeron Processors
95 32nm Atom Processors
103 45nm Xeon Processors 5400 Quad-Core
109 45nm Xeon Processors 5200 Dual-Core
116 45nm Atom Processors
134 45nm Core2 Processors
145 45nm Core2 Quad Processors
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| D | fam15h_power.rst | 6 * AMD Family 15h Processors
8 * AMD Family 16h Processors
16 - BIOS and Kernel Developer's Guide (BKDG) For AMD Family 15h Processors
17 - BIOS and Kernel Developer's Guide (BKDG) For AMD Family 16h Processors
33 of AMD Family 15h and 16h processors via TDP algorithm.
35 For AMD Family 15h and 16h processors the following power values can
55 On multi-node processors the calculated value is for the entire
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| D | peci-dimmtemp.rst | 8 * Intel Xeon E5/E7 v3 server processors
16 * Intel Xeon E5/E7 v4 server processors
22 * Intel Xeon Scalable server processors
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| D | peci-cputemp.rst | 8 * Intel Xeon E5/E7 v3 server processors
16 * Intel Xeon E5/E7 v4 server processors
22 * Intel Xeon Scalable server processors
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| /Documentation/arch/arc/ |
| D | arc.rst | 3 Linux kernel for ARC processors
10 ARC processors and relevant open source projects.
16 - `<https://github.com/foss-for-synopsys-dwc-arc-processors>`_ -
18 ARC processors. Some of the projects are forks of various upstream projects,
21 as open source for use on ARC Processors.
23 - `Official Synopsys ARC Processors website
26 Manual, AKA PRM for ARC HS processors
34 Important note on ARC processors configurability
37 ARC processors are highly configurable and several configurable options
52 Building the Linux kernel for ARC processors
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| /Documentation/admin-guide/hw-vuln/ |
| D | cross-thread-rsb.rst | 7 Certain AMD and Hygon processors are subject to a cross-thread return address
18 Affected processors
23 - AMD Family 17h processors
24 - Hygon Family 18h processors
38 Affected SMT-capable processors support 1T and 2T modes of execution when SMT
46 In affected processors, the return address predictor (RAP) is partitioned
61 An attack can be mounted on affected processors by performing a series of CALL
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| D | special-register-buffer-data-sampling.rst | 17 Affected processors
23 in the following list, with the exception of the listed processors
25 latter class of processors are only affected when Intel TSX is enabled
70 accesses from other logical processors will be delayed until the special
78 #. Executing RDRAND at the same time on multiple logical processors will be
83 logical processors that miss their core caches, with an impact similar to
88 Software Guard Extensions (Intel SGX) enclaves. On logical processors that
91 processors memory accesses. The opt-out mechanism does not affect Intel SGX
106 for other logical processors.
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| D | processor_mmio_stale_data.rst | 49 processors, MMIO primary reads will return 64 bytes of data to the core fill
61 processors affected by FBSDP, this may expose stale data from the fill buffers
67 into client core fill buffers, processors affected by MFBDS can leak data from
77 Affected Processors
80 processors for the server market (excluding Intel Xeon E3 processors) are
83 Below is the list of affected Intel processors [#f1]_:
115 Newer processors and microcode update on existing affected processors added new
130 values as part of MD_CLEAR operations. Processors that do not
135 IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]. On such processors, the FB_CLEAR_DIS
137 FB_CLEAR action. Not all processors that support FB_CLEAR will support
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| D | vmscape.rst | 13 Affected processors
18 **Intel processors:**
26 **AMD processors:**
29 ** Hygon processors:**
109 Force vulnerability detection and mitigation even on processors that are
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| D | reg-file-data-sampling.rst | 11 Affected Processors
13 Below is the list of affected Intel processors [#f1]_:
58 Newer processors and microcode update on existing affected processors added new
103 .. [#f1] Affected Processors
104 …ontent/www/us/en/developer/topic-technology/software-security-guidance/processors-affected-consoli…
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| D | multihit.rst | 4 iTLB multihit is an erratum where some processors may incur a machine check
12 Affected processors
18 - non-Intel processors
22 - Intel processors that have the PSCHANGE_MC_NO bit set in the
41 of the page tables. Modern processors use virtual memory, a technique that creates
42 the illusion of a very large memory for processors. This virtual space is split
47 processors include a structure, called TLB, that caches recent translations.
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | intel,ixp4xx-interrupt.yaml | 8 title: Intel IXP4xx XScale Networking Processors Interrupt Controller
14 This interrupt controller is found in the Intel IXP4xx processors.
15 Some processors have 32 interrupts, some have up to 64 interrupts.
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,corstone1000.yaml | 16 processors.
18 Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
19 systems for M-Class (or other) processors for adding sensors, connectivity,
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| /Documentation/arch/powerpc/ |
| D | ptrace.rst | 6 processors:
14 that's extendable and that covers both BookE and server processors, so
23 BookE processors don't have restrictions here, but server processors have
87 that the BookE supports. COMEFROM breakpoints available in server processors
137 - set a watchpoint in server processors (BookS)::
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| D | elf_hwcaps.rst | 147 The processor supports the v2.05 userlevel architecture. Processors
160 The processor supports the v2.06 userlevel architecture. Processors
182 The processor supports the v2.07 userlevel architecture. Processors
209 The processor supports the v3.0B / v3.0C userlevel architecture. Processors
228 The processor supports the v3.1 userlevel architecture. Processors
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| /Documentation/devicetree/bindings/timer/ |
| D | intel,ixp4xx-timer.yaml | 8 title: Intel IXP4xx XScale Networking Processors Timers
13 description: This timer is found in the Intel IXP4xx processors.
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| D | csky,mptimer.txt | 2 C-SKY Multi-processors Timer
5 C-SKY multi-processors timer is designed for C-SKY SMP system and the
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| /Documentation/devicetree/bindings/hwlock/ |
| D | qcom-hwspinlock.yaml | 13 The hardware block provides mutexes utilized between different processors on
14 the SoC as part of the communication protocol used by these processors.
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| /Documentation/devicetree/bindings/mailbox/ |
| D | hisilicon,hi3660-mailbox.txt | 4 are passed between processors, including application & communication
5 processors, MCU, HIFI, etc. Each channel is unidirectional and accessed
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | st-rproc.txt | 4 This binding provides support for adjunct processors found on ST SoCs.
6 Co-processors can be controlled from the bootloader or the primary OS. If
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| /Documentation/devicetree/bindings/arm/keystone/ |
| D | ti,sci.yaml | 13 Texas Instrument's processors including those belonging to Keystone generation
14 of processors have separate hardware entity which is now responsible for the
21 on multiple processors including ones running Linux.
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| /Documentation/devicetree/bindings/reserved-memory/ |
| D | qcom,rmtfs-mem.yaml | 11 purpose of describing the shared memory region used for remote processors to
43 Array of vmids of the remote processors, to set up memory protection
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| /Documentation/devicetree/bindings/gpio/ |
| D | intel,ixp4xx-gpio.yaml | 7 title: Intel IXP4xx XScale Networking Processors GPIO Controller
11 processors. It supports 16 GPIO lines.
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