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/Documentation/devicetree/bindings/soc/qcom/
Dqcom,apr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
20 - qcom,apr
21 - qcom,apr-v2
22 - qcom,gpr
24 power-domains:
27 qcom,apr-domain:
31 Selects the processor domain for apr
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Dqcom,apr-services.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,apr-services.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
39 qcom,protection-domain:
40 $ref: /schemas/types.yaml#/definitions/string-array
42 Protection domain service name and path for APR service (if supported).
51 - reg
/Documentation/ABI/testing/
Dsysfs-kernel-iommu_groups5 Description: /sys/kernel/iommu_groups/ contains a number of sub-
7 name of the sub-directory matches the iommu_group_id()
23 output direct-mapped, MSI, non mappable regions. Each
29 USB devices it is now exposed as "direct-relaxable" instead
38 domain in use by iommu for this group. See include/linux/iommu.h
45 DMA-FQ As above, but using batched invalidation to lazily
47 overhead at the cost of reduced memory protection.
50 but zero protection.
54 The default domain type of a group may be modified only when
56 - The device in the group is not bound to any device driver.
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Dconfigfs-tsm4 Contact: linux-coco@lists.linux.dev
7 protection this should include a nonce, but the kernel does not
13 Contact: linux-coco@lists.linux.dev
23 Contact: linux-coco@lists.linux.dev
30 "cert_table" from SEV-ES Guest-Hypervisor Communication Block
32 https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/specifications/56421.pdf
37 Contact: linux-coco@lists.linux.dev
49 Contact: linux-coco@lists.linux.dev
51 (RO) A name for the format-specification of @outblob like
57 https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/specifications/56860.pdf
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/Documentation/devicetree/bindings/sound/
Dqcom,q6core.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 - $ref: /schemas/soc/qcom/qcom,apr-services.yaml#
19 - qcom,q6core
22 - compatible
27 - |
28 #include <dt-bindings/soc/qcom,apr.h>
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Dqcom,q6prm.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 - $ref: /schemas/soc/qcom/qcom,apr-services.yaml#
19 - qcom,q6prm
21 clock-controller:
22 $ref: /schemas/sound/qcom,q6dsp-lpass-clocks.yaml#
27 - compatible
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Dqcom,q6adm.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 - $ref: /schemas/soc/qcom/qcom,apr-services.yaml#
19 - qcom,q6adm
23 $ref: /schemas/sound/qcom,q6adm-routing.yaml#
28 - compatible
29 - routing
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Dqcom,q6asm.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 - $ref: /schemas/soc/qcom/qcom,apr-services.yaml#
19 - qcom,q6asm
23 $ref: /schemas/sound/qcom,q6asm-dais.yaml#
28 - compatible
29 - dais
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Dqcom,q6apm.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 - $ref: dai-common.yaml#
15 - $ref: /schemas/soc/qcom/qcom,apr-services.yaml#
20 - qcom,q6apm
24 $ref: /schemas/sound/qcom,q6apm-lpass-dais.yaml#
30 $ref: /schemas/sound/qcom,q6apm-dai.yaml#
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Dqcom,q6afe.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 - $ref: /schemas/soc/qcom/qcom,apr-services.yaml#
19 - qcom,q6afe
21 clock-controller:
22 $ref: /schemas/sound/qcom,q6dsp-lpass-clocks.yaml#
28 $ref: /schemas/sound/qcom,q6dsp-lpass-ports.yaml#
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/Documentation/power/regulator/
Doverview.rst26 - Regulator
27 - Electronic device that supplies power to other devices.
31 Input Voltage -> Regulator -> Output Voltage
34 - PMIC
35 - Power Management IC. An IC that contains numerous
39 - Consumer
40 - Electronic device that is supplied power by a regulator.
41 Consumers can be classified into two types:-
52 - Power Domain
53 - Electronic circuit that is supplied its input power by the
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/Documentation/devicetree/bindings/pci/
Dpci.txt3 PCI Bus Binding to: IEEE Std 1275-1994
4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
14 - linux,pci-domain:
15 If present this property assigns a fixed PCI domain number to a host bridge,
18 host bridges in the system, otherwise potentially conflicting domain numbers
19 may be assigned to root buses behind different host bridges. The domain
21 - max-link-speed:
27 - reset-gpios:
30 - supports-clkreq:
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/Documentation/devicetree/bindings/power/
Dmediatek,power-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - MandyJH Liu <mandyjh.liu@mediatek.com>
11 - Matthias Brugger <mbrugger@suse.com>
17 IP cores belonging to a power domain should contain a 'power-domains'
18 property that is a phandle for SCPSYS node representing the domain.
22 pattern: '^power-controller(@[0-9a-f]+)?$'
26 - mediatek,mt6795-power-controller
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/Documentation/devicetree/bindings/rtc/
Dst,stm32-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/st,stm32-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gabriel Fernandez <gabriel.fernandez@foss.st.com>
15 - st,stm32-rtc
16 - st,stm32h7-rtc
17 - st,stm32mp1-rtc
18 - st,stm32mp25-rtc
27 clock-names:
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/Documentation/admin-guide/hw-vuln/
Dsrso.rst1 .. SPDX-License-Identifier: GPL-2.0
8 known scenario of poisoning CPU functional units - the Branch Target
9 Buffer (BTB) and Return Address Predictor (RAP) in this case - and then
10 tricking the elevated privilege domain (the kernel) into leaking
14 Return Address Stack/Return Stack Buffer). In some cases, a non-architectural
20 but the concern is that an attacker can mis-train the CPU BTB to predict
21 non-architectural CALL instructions in kernel space and use this to
23 leading to information disclosure via a speculative side-channel.
25 The issue is tracked under CVE-2023-20569.
28 -------------------
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Dl1tf.rst1 L1TF - L1 Terminal Fault
10 -------------------
15 - Processors from AMD, Centaur and other non Intel vendors
17 - Older processor models, where the CPU family is < 6
19 - A range of Intel ATOM processors (Cedarview, Cloverview, Lincroft,
22 - The Intel XEON PHI family
24 - Intel processors which have the ARCH_CAP_RDCL_NO bit set in the
33 ------------
38 CVE-2018-3615 L1 Terminal Fault SGX related aspects
39 CVE-2018-3620 L1 Terminal Fault OS, SMM related aspects
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/Documentation/devicetree/bindings/clock/
Dst,stm32h7-rcc.txt6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32h743-rcc"
13 - reg: should be register base and length as documented in the
16 - #reset-cells: 1, see below
18 - #clock-cells : from common clock binding; shall be set to 1
20 - clocks: External oscillator clock phandle
21 - high speed external clock signal (HSE)
22 - low speed external clock signal (LSE)
23 - external I2S clock (I2S_CKIN)
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/Documentation/admin-guide/
Dthunderbolt.rst1 .. SPDX-License-Identifier: GPL-2.0
22 is expected to be accompanied with an IOMMU based DMA protection.
25 -----------------------------------
27 should be a userspace tool that handles all the low-level details, keeps
31 found in ``Documentation/ABI/testing/sysfs-bus-thunderbolt``.
35 ``/etc/udev/rules.d/99-local.rules``::
89 the Thunderbolt domain the host controller manages. There is typically
90 one domain per Thunderbolt host controller.
102 -----------------------------------------------------------------
105 /sys/bus/thunderbolt/devices/0-1/authorized - 0
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Dcgroup-v2.rst1 .. _cgroup-v2:
11 conventions of cgroup v2. It describes all userland-visible aspects
14 v1 is available under :ref:`Documentation/admin-guide/cgroup-v1/index.rst <cgroup-v1>`.
19 1-1. Terminology
20 1-2. What is cgroup?
22 2-1. Mounting
23 2-2. Organizing Processes and Threads
24 2-2-1. Processes
25 2-2-2. Threads
26 2-3. [Un]populated Notification
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/Documentation/devicetree/bindings/memory-controllers/
Dsnps,dw-umctl2-ddrc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Michal Simek <michal.simek@amd.com>
17 16-bits or 32-bits or 64-bits wide.
20 controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
26 - deprecated: true
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/Documentation/devicetree/bindings/dma/
Dti-edma.txt8 ------------------------------------------------------------------------------
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
18 - #dma-cells: Should be set to <2>. The first number is the DMA request
20 - reg: Memory map of eDMA CC
21 - reg-names: "edma3_cc"
22 - interrupts: Interrupt lines for CCINT, MPERR and CCERRINT.
23 - interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
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/Documentation/mm/
Dmultigen_lru.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Multi-Gen LRU
6 The multi-gen LRU is an alternative LRU implementation that optimizes
14 ----------
20 * Simple self-correcting heuristics
23 implementations. In the multi-gen LRU, each generation represents a
25 (time-based) common frame of reference and therefore help make better
41 choices; thus self-correction is necessary.
43 The benefits of simple self-correcting heuristics are self-evident.
51 -----------
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/Documentation/security/
Dsnp-tdx-threat-model.rst17 the kernel through various networking or limited HW-specific exposed
20 and discuss the proposed protection mechanisms for the Linux kernel.
48 additional mechanisms to control guest-host page mapping. More details on
49 the x86-specific solutions can be found in
50 :doc:`Intel Trust Domain Extensions (TDX) </arch/x86/tdx>` and
51 …https://www.amd.com/system/files/techdocs/sev-snp-strengthening-vm-isolation-with-integrity-protec…
56 that acts as a security manager. The host-side virtual machine monitor
63 In the following diagram, the "<--->" lines represent bi-directional
67 +-------------------+ +-----------------------+
68 | CoCo guest VM |<---->| |
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/Documentation/ABI/stable/
Dsysfs-driver-mlxreg-io1 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_health
6 0 - health failed, 2 - health OK, 3 - ASIC in booting state.
10 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld1_version
11 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld2_version
20 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/fan_dir
25 forward direction - relevant bit is set 0;
26 reversed direction - relevant bit is set 1.
30 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_version
39 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/jtag_enable
43 Description: These files enable and disable the access to the JTAG domain.
[all …]
/Documentation/virt/kvm/arm/
Dpviommu.rst1 .. SPDX-License-Identifier: GPL-2.0
30 --------------------------------------
32 Attach a device to a domain, previously allocated from ``KVM_PVIOMMU_OP_ALLOC_DOMAIN``
34 +---------------------+-------------------------------------------------------------+
36 +---------------------+-------------------------------------------------------------+
38 +---------------------+----------+--------------------------------------------------+
40 +---------------------+----------+----+---------------------------------------------+
42 | +----------+----+---------------------------------------------+
44 | +----------+----+---------------------------------------------+
46 | +----------+----+---------------------------------------------+
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