Searched full:pulse (Results 1 – 25 of 137) sorted by relevance
123456
| /Documentation/devicetree/bindings/regulator/ |
| D | richtek,rtmv20-regulator.yaml | 36 richtek,ld-pulse-delay-us:
38 load current pulse delay in microsecond after strobe pin pulse high.
43 richtek,ld-pulse-width-us:
45 Load current pulse width in microsecond after strobe pin pulse high.
52 Fsin1 pulse high delay in microsecond after vsync signal pulse high.
59 Fsin1 pulse high width in microsecond after vsync signal pulse high.
66 Fsin2 pulse high delay in microsecond after vsync signal pulse high.
73 Fsin2 pulse high width in microsecond after vsync signal pulse high.
78 richtek,es-pulse-width-us:
79 description: Eye safety function pulse width limit in microsecond.
|
| /Documentation/devicetree/bindings/i2c/ |
| D | st,sti-i2c.yaml | 37 st,i2c-min-scl-pulse-width-us:
39 The minimum valid SCL pulse width that is allowed through the
42 st,i2c-min-sda-pulse-width-us:
44 The minimum valid SDA pulse width that is allowed through the
69 st,i2c-min-scl-pulse-width-us = <0>;
70 st,i2c-min-sda-pulse-width-us = <5>;
|
| /Documentation/driver-api/media/ |
| D | rc-core.rst | 33 hardware. When the carrier is switched on, it is called *PULSE*.
37 *PULSE* and *SPACE* events, each with a given duration.
40 *PULSE* and *SPACE* events depend on the protocol.
42 start with a 9ms *PULSE* and a 4.5ms SPACE. It then transmits 16 bits of
45 with 560µs *PULSE* followed by 1690µs *SPACE* and a bit "0" is modulated
46 with 560µs *PULSE* followed by 560µs *SPACE*.
49 signal in a sequence of *PULSE/SPACE* events, filtering out the carrier
52 of time it receives *PULSE/SPACE* events.
57 microcontroller that decode the *PULSE/SPACE* sequence and return scan
|
| /Documentation/devicetree/bindings/memory-controllers/ |
| D | atmel,ebi.txt | 87 - atmel,smc-ncs-rd-pulse-ns
88 - atmel,smc-nrd-pulse-ns
89 - atmel,smc-ncs-wr-pulse-ns
90 - atmel,smc-nwe-pulse-ns
128 atmel,smc-ncs-rd-pulse-ns = <84>;
129 atmel,smc-ncs-wr-pulse-ns = <84>;
130 atmel,smc-nrd-pulse-ns = <76>;
131 atmel,smc-nwe-pulse-ns = <76>;
|
| /Documentation/w1/masters/ |
| D | omap-hdq.rst | 26 initialization pulse.In HDQ mode, the firmware does not require the host to
27 create an initialization pulse to the slave.However, the slave can be reset by
28 using an initialization pulse (also referred to as a break pulse).The slave
29 does not respond with a presence pulse as it does in the 1-Wire protocol.
|
| /Documentation/devicetree/bindings/thermal/ |
| D | nvidia,tegra124-soctherm.yaml | 91 throttling depth of pulse skippers, it's the percentage
99 of pulse skippers, which used to throttle clock frequencies. It
115 level of pulse skippers, which used to throttle clock
264 * the HW will skip cpu clock's pulse in 85% depth,
265 * skip gpu clock's pulse in 85% level
277 * the HW will skip cpu clock's pulse in 50% depth,
278 * skip gpu clock's pulse in 50% level
291 * settings to skip cpu pulse.
326 * the HW will skip cpu clock's pulse in HIGH level
337 * the HW will skip cpu clock's pulse in MED level
[all …]
|
| /Documentation/devicetree/bindings/sound/ |
| D | awinic,aw8738.yaml | 14 (set using one-wire pulse control). The mode configures the speaker-guard
26 GPIO used for one-wire pulse control. The pin is typically called SHDN
32 description: Operation mode (number of pulses for one-wire pulse control)
|
| D | microchip,sama7g5-pdmc.yaml | 7 title: Microchip Pulse Density Microphone Controller
13 The Microchip Pulse Density Microphone Controller (PDMC) interfaces up to 4
14 digital microphones having Pulse Density Modulated (PDM) outputs.
|
| D | everest,es8326.yaml | 81 Bit(0-3) 0 means irq pulse equals 512*internal clock
82 1 means irq pulse equals 1024*internal clock
84 7 means irq pulse equals 65536*internal clock
|
| /Documentation/devicetree/bindings/leds/ |
| D | allwinner,sun50i-a100-ledc.yaml | 70 description: Length of high pulse when transmitting a "0" bit
74 description: Length of low pulse when transmitting a "0" bit
78 description: Length of high pulse when transmitting a "1" bit
82 description: Length of low pulse when transmitting a "1" bit
|
| /Documentation/devicetree/bindings/mfd/ |
| D | rohm,bd9571mwv.yaml | 55 rohm,rstbmode-pulse:
58 The RSTB signal is configured for pulse mode, to accommodate a momentary
95 - rohm,rstbmode-pulse
115 rohm,rstbmode-pulse;
|
| /Documentation/ABI/testing/ |
| D | sysfs-class-rc-nuvoton | 7 It starts with a pulse, followed by a space, pulse etc.
|
| /Documentation/userspace-api/media/rc/ |
| D | lirc-dev-intro.rst | 94 The driver returns a sequence of pulse and space codes to userspace,
131 .. _lirc-mode-pulse:
135 In pulse mode, a sequence of pulse/space integer values are written to the
138 The values are alternating pulse and space lengths, in microseconds. The
139 first and last entry must be a pulse, so there must be an odd number
163 to the LIRC device, this program will be called for each pulse, space or
|
| D | lirc-write.rst | 47 When in :ref:`LIRC_MODE_PULSE <lirc-mode-PULSE>` mode, the data written to
48 the chardev is a pulse/space sequence of integer values. Pulses and spaces
50 with a pulse, therefore, the data must always include an uneven number of
|
| D | lirc-get-features.rst | 47 .. _LIRC-CAN-REC-PULSE:
52 :ref:`LIRC_MODE_PULSE <lirc-mode-pulse>` can only be used for transmitting.
146 .. _LIRC-CAN-SEND-PULSE:
151 :ref:`LIRC_MODE_PULSE <lirc-mode-pulse>`. This implies that
|
| /Documentation/userspace-api/media/cec/ |
| D | cec-pin-error-inj.rst | 53 # tx-custom-low-usecs <usecs> define the 'low' time for the custom pulse
54 # tx-custom-high-usecs <usecs> define the 'high' time for the custom pulse
55 # tx-custom-pulse transmit the custom pulse once the bus is idle
64 # <op>[,<mode>] tx-custom-bit <bit> send the custom pulse instead of this bit
65 # <op>[,<mode>] tx-short-start send a start pulse that's too short
66 # <op>[,<mode>] tx-long-start send a start pulse that's too long
67 # <op>[,<mode>] tx-custom-start send the custom pulse instead of the start pulse
311 This defines the duration in microseconds that the custom pulse pulls
315 This defines the duration in microseconds that the custom pulse keeps the
317 The default is 1000 microseconds. The total period of the custom pulse is
[all …]
|
| /Documentation/hwmon/ |
| D | g760a.rst | 30 from the measured speed pulse period by assuming again a 32kHz clock
31 source and a 2 pulse-per-revolution fan.
|
| /Documentation/devicetree/bindings/memory-controllers/ddr/ |
| D | jedec,lpddr3-timings.yaml | 36 CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds.
41 CKE minimum pulse width during SELF REFRESH (low pulse width during
|
| /Documentation/driver-api/ |
| D | reset.rst | 39 is self-clearing and can be used to trigger a predetermined pulse on the
109 Consumer drivers use reset_control_reset() to trigger a reset pulse on a
112 requesting a pulse from any consumer driver will reset all connected
116 shared, but for those only the first trigger request causes an actual pulse to
159 assert or deassert reset signals, to trigger a reset pulse on a reset line, or
185 reset_control_deassert(), trigger a reset pulse using reset_control_reset(), or
|
| D | miscellaneous.rst | 24 Pulse-Width Modulation (PWM)
27 Pulse-width modulation is a modulation technique primarily used to
|
| /Documentation/devicetree/bindings/ptp/ |
| D | fsl,ptp.yaml | 69 description: Fixed interval period pulse generator.
73 description: Fixed interval period pulse generator.
78 Fixed interval period pulse generator.
104 Pulse Per Second (PPS) signal, since this will be offered to the PPS
|
| /Documentation/admin-guide/media/ |
| D | cec.rst | 41 - Pulse-Eight: the pulse8-cec driver implements the following module option:
47 module option of the Pulse-Eight driver. The hardware supports it, but I
86 Note that the libcec library (https://github.com/Pulse-Eight/libcec) supports
160 utility to create the ``/dev/cecX`` devices. Support for the Pulse-Eight
172 For Pulse-Eight make /lib/systemd/system/pulse8-cec-inputattach@.service::
199 …ExecStart=/bin/bash -c 'for d in /dev/serial/by-id/usb-Pulse-Eight*; do /usr/bin/inputattach --dae…
247 1) Get a Pulse-Eight USB CEC dongle, connect an HDMI cable from your
248 device to the Pulse-Eight, but do not connect the Pulse-Eight to
251 Now configure the Pulse-Eight dongle::
268 The Pulse-Eight should see the <Image View On> message. If not,
[all …]
|
| /Documentation/devicetree/bindings/mtd/ |
| D | lpc32xx-slc.txt | 15 - nxp,wwidth: Write pulse width (W_WIDTH)
18 - nxp,rwidth: Read pulse width (R_WIDTH)
|
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | csky,apb-intc.txt | 36 - csky,support-pulse-signal:
38 Description: to support pulse signal flag
|
| /Documentation/devicetree/bindings/watchdog/ |
| D | aspeed,ast2400-wdt.yaml | 67 aspeed,ext-pulse-duration:
70 The duration, in microseconds, of the pulse emitted on the external signal
84 the node, set the pulse polarity to active-high. If aspeed,ext-active-high
|
123456