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/Documentation/devicetree/bindings/pwm/
Dpwm-sifive.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive PWM controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 Unlike most other PWM controllers, the SiFive PWM controller currently
15 only supports one period for all channels in the PWM. All PWMs need to
16 run at the same period. The period also has significant restrictions on
18 achievable period. PWM RTL that corresponds to the IP block version
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Dimx-tpm-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/imx-tpm-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX TPM PWM controller
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 The TPM counter and period counter are shared between multiple
16 channels, so all channels should use same period setting.
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Dmicrochip,corepwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Conor Dooley <conor.dooley@microchip.com>
16 https://www.microsemi.com/existing-parts/parts/152118
19 - $ref: pwm.yaml#
24 - const: microchip,corepwm-rtl-v4
32 "#pwm-cells":
37 microchip,sync-update-mask:
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Dpwm.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PWM controllers (providers)
10 - Thierry Reding <thierry.reding@gmail.com>
16 pattern: "^pwm(@.*|-([0-9]|[1-9][0-9]+))?$"
18 "#pwm-cells":
20 Number of cells in a PWM specifier. Typically the cells represent, in
21 order: the chip-relative PWM number, the PWM period in nanoseconds and
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Dmarvell,pxa-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/marvell,pxa-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell PXA PWM
10 - Duje Mihanović <duje.mihanovic@skole.hr>
13 - $ref: pwm.yaml#
18 - marvell,pxa250-pwm
19 - marvell,pxa270-pwm
20 - marvell,pxa168-pwm
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Dpwm-lp3943.txt1 TI/National Semiconductor LP3943 PWM controller
4 - compatible: "ti,lp3943-pwm"
5 - #pwm-cells: Should be 2. See pwm.yaml in this directory for a
7 Note that this hardware limits the period length to the
9 - ti,pwm0 or ti,pwm1: Output pin number(s) for PWM channel 0 or 1.
17 PWM 0 is for RGB LED brightness control
18 PWM 1 is for brightness control of LP8557 backlight device
26 * PWM 0 : output 8, 9 and 10
27 * PWM 1 : output 15
29 pwm3943: pwm {
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Dadi,axi-pwmgen.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pwm/adi,axi-pwmgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI PWM generator
10 - Michael Hennerich <Michael.Hennerich@analog.com>
11 - Nuno Sá <nuno.sa@analog.com>
14 The Analog Devices AXI PWM generator can generate PWM signals
15 with variable pulse width and period.
20 - $ref: pwm.yaml#
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Dpwm-st.txt1 STMicroelectronics PWM driver bindings
2 --------------------------------------
5 - compatible : "st,pwm"
6 - #pwm-cells : Number of cells used to specify a PWM. First cell
7 specifies the per-chip index of the PWM to use and the
8 second cell is the period in nanoseconds - fixed to 2
10 - reg : Physical base address and length of the controller's
12 - pinctrl-names: Set to "default".
13 - pinctrl-0: List of phandles pointing to pin configuration nodes
14 for PWM module.
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Dpwm.txt1 Specifying PWM information for devices
4 1) PWM user nodes
5 -----------------
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
16 PWM properties should be named "pwms". The exact meaning of each pwms
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/Documentation/driver-api/
Dpwm.rst2 Pulse Width Modulation (PWM) interface
5 This provides an overview about the Linux PWM interface
9 the Linux PWM API (although they could). However, PWMs are often
12 this kind of flexibility the generic PWM API exists.
15 ----------------
17 Users of the legacy PWM API use unique IDs to refer to PWM devices.
19 Instead of referring to a PWM device via its unique ID, board setup code
20 should instead register a static mapping that can be used to match PWM
24 PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight", NULL,
36 ----------
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Dmiscellaneous.rst4 .. kernel-doc:: include/linux/parport.h
7 .. kernel-doc:: drivers/parport/ieee1284.c
10 .. kernel-doc:: drivers/parport/share.c
13 .. kernel-doc:: drivers/parport/daisy.c
19 .. kernel-doc:: drivers/tty/serial/8250/8250_core.c
24 Pulse-Width Modulation (PWM)
27 Pulse-width modulation is a modulation technique primarily used to
30 The PWM framework provides an abstraction for providers and consumers of
31 PWM signals. A controller that provides one or more PWM signals is
33 are expected to embed this structure in a driver-specific structure.
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/Documentation/ABI/testing/
Dsysfs-class-pwm1 What: /sys/class/pwm/
6 The pwm/ class sub-directory belongs to the Generic PWM
7 Framework and provides a sysfs interface for using PWM
10 What: /sys/class/pwm/pwmchip<N>/
15 A /sys/class/pwm/pwmchipN directory is created for each
16 probed PWM controller/chip where N is the base of the
17 PWM chip.
19 What: /sys/class/pwm/pwmchip<N>/npwm
24 The number of PWM channels supported by the PWM chip.
26 What: /sys/class/pwm/pwmchip<N>/export
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/Documentation/devicetree/bindings/sound/
Dti,tas5086.txt1 Texas Instruments TAS5086 6-channel PWM Processor
5 - compatible: Should contain "ti,tas5086".
6 - reg: The i2c address. Should contain <0x1b>.
10 - reset-gpio: A GPIO spec to define which pin is connected to the
14 - ti,charge-period: This property should contain the time in microseconds
15 that closely matches the external single-ended
16 split-capacitor charge period. The hardware chip
17 waits for this period of time before starting the
18 PWM signals. This helps reduce pops and clicks.
23 - ti,mid-z-channel-X: Boolean properties, X being a number from 1 to 6.
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/Documentation/devicetree/bindings/leds/backlight/
Dlp855x-backlight.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/lp855x-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Artur Weber <aweber.kernel@gmail.com>
15 - ti,lp8550
16 - ti,lp8551
17 - ti,lp8552
18 - ti,lp8553
19 - ti,lp8555
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/Documentation/devicetree/bindings/clock/
Dnvidia,tegra124-dfll.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 the fast CPU cluster. It consists of a free-running voltage controlled
10 communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
13 - compatible : should be one of:
14 - "nvidia,tegra124-dfll": for Tegra124
15 - "nvidia,tegra210-dfll": for Tegra210
16 - reg : Defines the following set of registers, in the order listed:
17 - registers for the DFLL control logic.
18 - registers for the I2C output logic.
19 - registers for the integrated I2C master controller.
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Dpwm-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/pwm-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: An external clock signal driven by a PWM pin.
10 - Philipp Zabel <p.zabel@pengutronix.de>
14 const: pwm-clock
16 '#clock-cells':
19 clock-frequency:
20 description: Exact output frequency, in case the PWM period is not exact
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/Documentation/devicetree/bindings/input/
Dpwm-vibrator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/pwm-vibrator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PWM vibrator
10 - Sebastian Reichel <sre@kernel.org>
13 Registers a PWM device as vibrator. It is expected, that the vibrator's
14 strength increases based on the duty cycle of the enable PWM channel
17 The binding supports an optional direction PWM channel, that can be
23 const: pwm-vibrator
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/Documentation/hwmon/
Dg760a.rst6 * Global Mixed-mode Technology Inc. G760A
12 http://www.gmt.com.tw/product/datasheet/EDS-760A.pdf
17 -----------
19 The GMT G760A Fan Speed PWM Controller is connected directly to a fan
20 and performs closed-loop control of the fan speed.
22 The fan speed is programmed by setting the period via 'pwm1' of two
23 consecutive speed pulses. The period is defined in terms of clock
26 Setting a period of 0 stops the fan; setting the period to 255 sets
30 from the measured speed pulse period by assuming again a 32kHz clock
31 source and a 2 pulse-per-revolution fan.
Dlm93.rst10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
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/Documentation/driver-api/backlight/
Dlp855x-driver.rst15 -----------
19 Brightness can be controlled by the pwm input or the i2c command.
28 Value: pwm based or register based
37 ------------------------
48 Platform specific PWM period value. unit is nano.
49 Only valid when brightness is pwm input mode.
68 .name = "lcd-bl",
75 2) lp8556 platform data: pwm input mode with default rom data::
/Documentation/devicetree/bindings/hwmon/
Dadt7475.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jean Delvare <jdelvare@suse.com>
23 https://www.onsemi.com/pub/Collateral/ADT7473-D.PDF
24 https://www.onsemi.com/pub/Collateral/ADT7475-D.PDF
25 https://www.onsemi.com/pub/Collateral/ADT7476-D.PDF
26 https://www.onsemi.com/pub/Collateral/ADT7490-D.PDF
34 - adi,adt7473
35 - adi,adt7475
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/Documentation/devicetree/bindings/gpio/
Dgpio-mvebu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mvebu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 - Andrew Lunn <andrew@lunn.ch>
16 - enum:
17 - marvell,armada-8k-gpio
18 - marvell,orion-gpio
20 - items:
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/Documentation/devicetree/bindings/display/
Dsolomon,ssd1307fb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Ripard <mripard@kernel.org>
11 - Javier Martinez Canillas <javierm@redhat.com>
17 - enum:
18 - solomon,ssd1305fb-i2c
19 - solomon,ssd1306fb-i2c
20 - solomon,ssd1307fb-i2c
21 - solomon,ssd1309fb-i2c
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/Documentation/leds/
Dleds-qcom-lpg.rst1 .. SPDX-License-Identifier: GPL-2.0
8 -----------
11 number of PWM channels, a programmable pattern lookup table and a RGB LED
15 individual LEDs, grouped together as RGB LEDs or otherwise be accessed as PWM
16 channels. The output of each PWM channel is routed to other hardware
19 The each PWM channel can operate with a period between 27us and 384 seconds and
31 --------------------------------
35 The pattern is a series of brightness and hold-time pairs, with the hold-time
39 transitions expected by the leds-trigger-pattern format, each entry in the
40 pattern must be followed a zero-length entry of the same brightness.
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/Documentation/devicetree/bindings/leds/
Dnxp,pca963x.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The NXP PCA963x are I2C-controlled LED drivers optimized for
15 individually controllable and has its own PWM controller.
19 - https://www.nxp.com/docs/en/data-sheet/PCA9632.pdf
20 - https://www.nxp.com/docs/en/data-sheet/PCA9633.pdf
21 - https://www.nxp.com/docs/en/data-sheet/PCA9634.pdf
22 - https://www.nxp.com/docs/en/data-sheet/PCA9635.pdf
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