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/Documentation/arch/arm/
Dporting.rst5 Taken from list archive at http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2001-July/00406…
8 -------------------
14 phys = virt - PAGE_OFFSET + PHYS_OFFSET
18 --------------------
23 the time when you call the decompressor code. You normally call
25 to be located in RAM, it can be in flash or other read-only or
26 read-write addressable medium.
29 Start address of zero-initialised work area for the decompressor.
30 This must be pointing at RAM. The decompressor will zero initialise
43 Physical address to place the initial RAM disk. Only relevant if
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Dtcm.rst2 ARM TCM (Tightly-Coupled Memory) handling in Linux
7 Some ARM SoCs have a so-called TCM (Tightly-Coupled Memory).
8 This is usually just a few (4-64) KiB of RAM inside the ARM
12 Harvard-architecture, so there is an ITCM (instruction TCM)
24 determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
32 place you put it, it will mask any underlying RAM from the
33 CPU so it is usually wise not to overlap any physical RAM with
52 - FIQ and other interrupt handlers that need deterministic
55 - Idle loops where all external RAM is set to self-refresh
56 retention mode, so only on-chip RAM is accessible by
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Dmemory.rst11 free for platforms to use, and which are used by generic code.
39 in proc-xscale.S to flush the whole data
53 ff800000 ffbfffff Permanent, fixed read-only mapping of the
59 VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space.
68 PAGE_OFFSET high_memory-1 Kernel direct-mapped RAM region.
69 This maps the platforms RAM, and typically
70 maps all platform RAM in a 1:1 relationship.
72 PKMAP_BASE PAGE_OFFSET-1 Permanent kernel mappings
76 MODULES_VADDR MODULES_END-1 Kernel module space
80 TASK_SIZE MODULES_VADDR-1 KASAn shadow memory when KASan is in use.
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/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra20-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
17 various performance-affecting settings beyond the obvious SDRAM configuration
23 const: nvidia,tegra20-emc
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Dnvidia,tegra124-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
22 const: nvidia,tegra124-mc
30 clock-names:
32 - const: mc
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Dnvidia,tegra30-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
39 const: nvidia,tegra30-mc
47 clock-names:
49 - const: mc
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Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
23 const: nvidia,tegra30-emc
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/Documentation/devicetree/bindings/misc/
Dnvidia,tegra20-apbmisc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - items:
17 - enum:
18 - nvidia,tegra210-apbmisc
19 - nvidia,tegra124-apbmisc
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/Documentation/fb/
Dcirrusfb.rst12 - SD64
13 - Piccolo
14 - Picasso
15 - Spectrum
16 - Alpine (GD-543x/4x)
17 - Picasso4 (GD-5446)
18 - GD-5480
19 - Laguna (GD-546x)
22 - PCI
23 - Zorro
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/Documentation/arch/arm/keystone/
Dknav-qmss.rst5 Driver source code path
11 multi-core Navigator. QMSS consist of queue managers, packed-data structure
12 processors(PDSP), linking RAM, descriptor pools and infrastructure
15 management of the packet queues. Packets are queued/de-queued by writing or
18 Linking RAM registers are used to link the descriptors which are stored in
19 descriptor RAM. Descriptor RAM is configurable as internal or external memory.
20 The QMSS driver manages the PDSP setups, linking RAM regions,
29 Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt
40 git://git.ti.com/keystone-rtos/qmss-lld.git
43 channels. This firmware is available under ti-keystone folder of
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/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/
Di2c.txt6 - compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c"
7 - reg : On CPM2 devices, the second resource doesn't specify the I2C
8 Parameter RAM itself, but the I2C_BASE field of the CPM2 Parameter RAM
10 - #address-cells : Should be one. The cell is the i2c device address with
12 - #size-cells : Should be zero.
13 - clock-frequency : Can be used to set the i2c clock frequency. If
17 - linux,i2c-index : Can be used to hard code an i2c bus number. By default,
19 - linux,i2c-class : Can be used to override the i2c class. The class is used
28 compatible = "fsl,mpc823-i2c",
29 "fsl,cpm1-i2c";
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/Documentation/admin-guide/
Dramoops.rst9 ------------
11 Ramoops is an oops/panic logger that writes its logs to RAM before the system
13 needs a system with persistent RAM so that the content of that area can
17 ----------------
56 to life (i.e. a watchdog triggered). In such cases, RAM may be somewhat
60 ----------------------
68 the kernel to use only the first 128 MB of memory, and place ECC-protected
74 ``Documentation/devicetree/bindings/reserved-memory/ramoops.yaml``.
77 reserved-memory {
78 #address-cells = <2>;
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/Documentation/admin-guide/pm/
Dsleep-states.rst1 .. SPDX-License-Identifier: GPL-2.0
13 Sleep states are global low-power states of the entire system in which user
14 space code cannot be executed and the overall system activity is significantly
28 Suspend-to-Idle
29 ---------------
31 This is a generic, pure software, light-weight variant of system suspend (also
34 I/O devices into low-power states (possibly lower-power than available in the
38 The system is woken up from this state by in-band interrupts, so theoretically
43 or :ref:`suspend-to-RAM <s2ram>`, or it can be used in addition to any of the
50 -------
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Dsuspend-flows.rst1 .. SPDX-License-Identifier: GPL-2.0
5 System Suspend Code Flows
12 At least one global system-wide transition needs to be carried out for the
14 :doc:`sleep states <sleep-states>`. Hibernation requires more than one
16 referred to as *system-wide suspend* (or simply *system suspend*) states, need
25 The kernel code flows associated with the suspend and resume transitions for
27 significant differences between the :ref:`suspend-to-idle <s2idle>` code flows
28 and the code flows related to the :ref:`suspend-to-RAM <s2ram>` and
31 The :ref:`suspend-to-RAM <s2ram>` and :ref:`standby <standby>` sleep states
33 boils down to the platform-specific actions carried out by the suspend and
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/Documentation/scsi/
DChangeLog.ncr53c8xx1 Sat May 12 12:00 2001 Gerard Roudier (groudier@club-internet.fr)
2 * version ncr53c8xx-3.4.3b
3 - Ensure LEDC bit in GPCNTL is cleared when reading the NVRAM.
4 Fix sent by Stig Telfer <stig@api-networks.com>.
5 - Define scsi_set_pci_device() as nil for kernel < 2.4.4.
7 Mon Feb 12 22:30 2001 Gerard Roudier (groudier@club-internet.fr)
8 * version ncr53c8xx-3.4.3
9 - Call pci_enable_device() as AC wants this to be done.
10 - Get both the BAR cookies actual and PCI BAR values.
12 - Merge changes for linux-2.4 that declare the host template
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/Documentation/devicetree/bindings/soc/loongson/
Dloongson,ls2k-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/loongson/loongson,ls2k-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-2 Power Manager controller
10 - Yinbo Zhu <zhuyinbo@loongson.cn>
15 - items:
16 - const: loongson,ls2k0500-pmc
17 - const: syscon
18 - items:
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/Documentation/devicetree/bindings/sound/
Dfsl,xcvr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viorel Suman <viorel.suman@nxp.com>
13 NXP XCVR (Audio Transceiver) is a on-chip functional module
23 - fsl,imx8mp-xcvr
24 - fsl,imx93-xcvr
25 - fsl,imx95-xcvr
29 - description: 20K RAM for code and data
30 - description: registers space
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/Documentation/power/
Dsuspend-and-cpuhotplug.rst2 Interaction of Suspend code (S3) with the CPU hotplug infrastructure
5 (C) 2011 - 2014 Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
8 I. Differences between CPU hotplug and Suspend-to-RAM
11 How does the regular CPU hotplug code differ from how the Suspend-to-RAM
12 infrastructure uses it internally? And where do they share common code?
14 Well, a picture is worth a thousand words... So ASCII art follows :-)
20 of describing where they take different paths and where they share code.
21 What happens when regular CPU hotplug and Suspend-to-RAM race with each other
24 On a high level, the suspend-resume cycle goes like this::
26 |Freeze| -> |Disable nonboot| -> |Do suspend| -> |Enable nonboot| -> |Thaw |
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/Documentation/networking/
Dgeneric-hdlc.rst1 .. SPDX-License-Identifier: GPL-2.0
14 - Normal (routed) and Ethernet-bridged (Ethernet device emulation)
16 - ARP support (no InARP support in the kernel - there is an
17 experimental InARP user-space daemon available on:
20 2. raw HDLC - either IP (IPv4) interface or Ethernet device emulation
25 Generic HDLC is a protocol driver only - it needs a low-level driver
28 Ethernet device emulation (using HDLC or Frame-Relay PVC) is compatible
40 gcc -O2 -Wall -o sethdlc sethdlc.c
66 - sets physical interface for a given port
67 if the card has software-selectable interfaces
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/Documentation/filesystems/
Dramfs-rootfs-initramfs.rst1 .. SPDX-License-Identifier: GPL-2.0
12 --------------
16 RAM-based filesystem.
32 The amount of code required to implement ramfs is tiny, because all the
39 ------------------
41 The older "ram disk" mechanism created a synthetic block device out of
42 an area of RAM and used it as backing store for a filesystem. This block
44 size. Using a ram disk also required unnecessarily copying memory from the
54 since all file access goes through the page and dentry caches. The RAM
57 Another reason ramdisks are semi-obsolete is that the introduction of
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/Documentation/devicetree/bindings/mtd/
Dmtd-physmap.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
10 - Rob Herring <robh@kernel.org>
17 - $ref: mtd.yaml#
18 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
23 - items:
24 - enum:
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/Documentation/arch/x86/
Dintel_txt.rst6 Technology (Intel(R) TXT), defines platform-level enhancements that
9 Intel TXT was formerly known by the code name LaGrande Technology (LT).
13 - Provides dynamic root of trust for measurement (DRTM)
14 - Data protection in case of improper shutdown
15 - Measurement and verification of launched environment
18 non-vPro systems. It is currently available on desktop systems
30 - LinuxTAG 2008:
31 http://www.linuxtag.org/2008/en/conf/events/vp-donnerstag.html
33 - TRUST2008:
34 http://www.trust-conference.eu/downloads/Keynote-Speakers/
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/Documentation/arch/arm64/
Dbooting.rst13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
20 hypervisor code, or it may just be a handful of instructions for
26 1. Setup and initialise the RAM
32 1. Setup and initialise RAM
33 ---------------------------
37 The boot loader is expected to find and initialise all RAM that the
40 to automatically locate and size all RAM, or it may use knowledge of
41 the RAM in the machine, or any other method the boot loader designer
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
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/Documentation/devicetree/bindings/memory-controllers/fsl/
Dimx8m-ddrc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
17 this process RAM itself becomes briefly inaccessible so actual frequency
18 switching is implemented by TF-A code which runs from a SRAM area.
27 - enum:
28 - fsl,imx8mn-ddrc
29 - fsl,imx8mm-ddrc
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/Documentation/devicetree/bindings/remoteproc/
Dqcom,rpm-proc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,rpm-proc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Konrad Dybcio <konradybcio@kernel.org>
12 - Stephan Gerhold <stephan@gerhold.net>
17 +--------------------------------------------+
18 | RPM subsystem (qcom,rpm-proc) |
20 reset | +---------------+ +-----+ +-----+ |
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