Searched full:rcc (Results 1 – 25 of 46) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ |
| D | st,stm32-rcc.txt | 4 The RCC IP is both a reset and a clock controller.
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
29 rcc: rcc@40023800 {
32 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
42 The secondary index is the bit number within the RCC register bank, starting
43 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
49 drivers of the RCC IP, macros are available to generate the index in
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| D | st,stm32mp1-rcc.yaml | 4 $id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml#
13 The RCC IP is both a reset and a clock controller.
14 RCC makes also power management (resume/supend and wakeup interrupt).
33 The index is the bit number within the RCC registers bank, starting from RCC
59 - st,stm32mp1-rcc-secure
60 - st,stm32mp1-rcc
61 - st,stm32mp13-rcc
86 - st,stm32mp1-rcc-secure
87 - st,stm32mp13-rcc
119 rcc: rcc@50000000 {
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| D | st,stm32h7-rcc.txt | 4 The RCC IP is both a reset and a clock controller.
11 "st,stm32h743-rcc"
31 rcc: reset-clock-controller@58024400 {
32 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
50 clocks = <&rcc TIM5_CK>;
59 The index is the bit number within the RCC registers bank, starting from RCC
70 resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
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| D | st,stm32mp25-rcc.yaml | 4 $id: http://devicetree.org/schemas/clock/st,stm32mp25-rcc.yaml#
13 The RCC hardware block is both a reset and a clock controller.
14 RCC makes also power management (resume/supend).
17 include/dt-bindings/clock/st,stm32mp25-rcc.h
18 include/dt-bindings/reset/st,stm32mp25-rcc.h
23 - st,stm32mp25-rcc
132 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
134 rcc: clock-controller@44200000 {
135 compatible = "st,stm32mp25-rcc";
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| /Documentation/devicetree/bindings/net/ |
| D | stm32-dwmac.yaml | 95 select RCC clock instead of ETH_REF_CLK. OR in RGMII mode when you want to select
96 RCC clock instead of ETH_CLK125.
101 set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
107 select RCC clock instead of ETH_REF_CLK.
168 clocks = <&rcc ETHMAC>,
169 <&rcc ETHTX>,
170 <&rcc ETHRX>,
171 <&rcc ETHSTP>,
172 <&rcc ETHCK_K>;
189 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
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| /Documentation/devicetree/bindings/i2c/ |
| D | st,stm32-i2c.yaml | 145 #include <dt-bindings/mfd/stm32f7-rcc.h>
153 resets = <&rcc 277>;
154 clocks = <&rcc 0 149>;
160 #include <dt-bindings/mfd/stm32f7-rcc.h>
168 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
169 clocks = <&rcc 1 CLK_I2C1>;
175 #include <dt-bindings/mfd/stm32f7-rcc.h>
186 clocks = <&rcc I2C2_K>;
187 resets = <&rcc I2C2_R>;
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| /Documentation/devicetree/bindings/display/ |
| D | st,stm32mp25-lvds.yaml | 88 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
89 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
95 clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>;
97 resets = <&rcc LVDS_R>;
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| D | st,stm32-dsi.yaml | 94 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
96 resets = <&rcc DSI_R>;
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| D | st,stm32-ltdc.yaml | 66 clocks = <&rcc LTDC_PX>;
68 resets = <&rcc LTDC_R>;
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| /Documentation/devicetree/bindings/rtc/ |
| D | st,stm32-rtc.yaml | 148 #include <dt-bindings/mfd/stm32f4-rcc.h>
153 clocks = <&rcc 1 CLK_RTC>;
154 assigned-clocks = <&rcc 1 CLK_RTC>;
155 assigned-clock-parents = <&rcc 1 CLK_LSE>;
167 clocks = <&rcc RTCAPB>, <&rcc RTC>;
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| /Documentation/devicetree/bindings/reset/ |
| D | st,stm32-rcc.txt | 4 The RCC IP is both a reset and a clock controller.
6 Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
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| D | st,stm32mp1-rcc.txt | 4 The RCC IP is both a reset and a clock controller.
6 Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
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| /Documentation/devicetree/bindings/sound/ |
| D | st,stm32-i2s.yaml | 92 clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
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| D | st,stm32-sai.yaml | 186 clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
198 clocks = <&rcc SAI2_K>;
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| /Documentation/devicetree/bindings/media/ |
| D | st,stm32-dma2d.yaml | 61 #include <dt-bindings/mfd/stm32f4-rcc.h>
66 resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
67 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
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| D | st,stm32-dcmipp.yaml | 75 resets = <&rcc DCMIPP_R>;
76 clocks = <&rcc DCMIPP_K>;
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| D | st,stm32-dcmi.yaml | 104 resets = <&rcc CAMITF_R>;
105 clocks = <&rcc DCMI>;
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| /Documentation/devicetree/bindings/net/can/ |
| D | st,stm32-bxcan.yaml | 85 #include <dt-bindings/mfd/stm32f4-rcc.h>
92 resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
93 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
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| /Documentation/devicetree/bindings/watchdog/ |
| D | st,stm32-iwdg.yaml | 59 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
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| /Documentation/devicetree/bindings/crypto/ |
| D | st,stm32-cryp.yaml | 70 clocks = <&rcc CRYP1>;
71 resets = <&rcc CRYP1_R>;
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| D | st,stm32-hash.yaml | 87 clocks = <&rcc HASH1>;
88 resets = <&rcc HASH1_R>;
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| /Documentation/devicetree/bindings/spi/ |
| D | st,stm32-spi.yaml | 78 clocks = <&rcc SPI2_K>;
79 resets = <&rcc SPI2_R>;
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| D | st,stm32-qspi.yaml | 75 clocks = <&rcc QSPI_K>;
76 resets = <&rcc QSPI_R>;
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| /Documentation/devicetree/bindings/bus/ |
| D | st,stm32-etzpc.yaml | 88 clocks = <&rcc USART2_K>;
89 resets = <&rcc USART2_R>;
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | st,stm32-pinctrl.yaml | 220 #include <dt-bindings/mfd/stm32f4-rcc.h>
233 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
250 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
260 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
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