Searched +full:read +full:- +full:delay (Results 1 – 25 of 159) sorted by relevance
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
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| D | ti,gpmc-child.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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| D | mvebu-devbus.txt | 9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
35 Read parameters:
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| /Documentation/devicetree/bindings/spi/ |
| D | cdns,qspi-nor-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for the Cadence QSPI controller.
10 See spi-peripheral-props.yaml for more info.
13 - Vaishnav Achath <vaishnav.a@ti.com>
16 # cdns,qspi-nor.yaml
17 cdns,read-delay:
20 Delay for read capture logic, in clock cycles.
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| D | spi-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
12 controller specific like delay in clock or data lines, etc. These properties
13 need to be defined in the peripheral node because they are per-peripheral and
19 - Mark Brown <broonie@kernel.org>
27 - minimum: 0
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| /Documentation/admin-guide/device-mapper/ |
| D | delay.rst | 2 dm-delay
5 Device-Mapper's "delay" target delays reads and/or writes
10 <device> <offset> <delay> [<write_device> <write_offset> <write_delay>
15 3: apply offset and delay to read, write and flush operations on device
17 6: apply offset and delay to device, also apply write_offset and write_delay
35 # Create mapped device named "delayed" delaying read, write and flush operations for 500ms.
37 dmsetup create delayed --table "0 `blockdev --getsz $1` delay $1 0 500"
46 dmsetup create delayed --table "0 `blockdev --getsz $1` delay $1 2048 0 $2 4096 400"
54 dmsetup create delayed --table "0 `blockdev --getsz $1` delay $1 0 50 $2 0 100 $1 0 333"
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| D | dm-flakey.rst | 2 dm-flakey
13 Also, consider using this in combination with the dm-delay target too,
14 which can delay reads and writes and/or send them to different
18 ----------------
28 Full pathname to the underlying block-device, or a
29 "major:minor" device-number.
43 All read I/O is failed with an error signalled.
48 Read I/O is handled correctly.
52 Read I/O is handled correctly.
65 The value (from 0-255) to write.
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| /Documentation/devicetree/bindings/mmc/ |
| D | sprd,sdhci-r11.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
16 const: sprd,sdhci-r11
27 - description: SDIO source clock
28 - description: gate clock for enabling/disabling the device
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| D | fsl-imx-esdhc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: sdhci-common.yaml#
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
25 - enum:
26 - fsl,imx25-esdhc
27 - fsl,imx35-esdhc
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| /Documentation/i2c/ |
| D | slave-testunit-backend.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 by Wolfram Sang <wsa@sang-engineering.com> in 2020
11 easy to obtain). Examples include multi-master testing, and SMBus Host Notify
21 # echo "slave-testunit 0x1030" > /sys/bus/i2c/devices/i2c-0/new_device
30 compatible = "slave-testunit";
39 When writing, the device consists of 4 8-bit registers and, except for some
43 .. csv-table::
49 0x03, DELAY, delay in n * 10ms until test is started
51 Using 'i2cset' from the i2c-tools package, the generic command looks like::
53 # i2cset -y <bus_num> <testunit_address> <CMD> <DATAL> <DATAH> <DELAY> i
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| /Documentation/devicetree/bindings/memory-controllers/ddr/ |
| D | jedec,lpddr3-timings.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
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| D | jedec,lpddr3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - samsung,K3QF2F20DB
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| /Documentation/translations/zh_CN/accounting/ |
| D | delay-accounting.rst | 1 .. include:: ../disclaimer-zh_CN.rst
3 :Original: Documentation/accounting/delay-accounting.rst
37 ----
58 ----
78 getdelays [-dilv] [-t tgid] [-p pid]
82 # ./getdelays -d -p 10
87 # ./getdelays -d -t 5
92 CPU count real total virtual total delay total delay average
94 IO count delay total delay average
96 SWAP count delay total delay average
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| /Documentation/hwmon/ |
| D | nsa320.rst | 22 Adam Baker <linux@baker-net.org.uk>
25 -----------
35 that contains 0x55 as a marker to indicate that data is being read correctly,
40 sysfs-Interface
41 ---------------
49 -----
52 provided kernel. Testing has shown that if the delay between chip select and
56 read twice corrupting the output. The above analysis is based upon a sample
57 of one unit but suggests that the Zyxel provided delay values include a
62 time to read the data from the device and when it does it reads both temp and
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| /Documentation/devicetree/bindings/mtd/ |
| D | orion-nand.txt | 4 - compatible : "marvell,orion-nand".
5 - reg : Base physical address of the NAND and length of memory mapped
9 - cle : Address line number connected to CLE. Default is 0
10 - ale : Address line number connected to ALE. Default is 1
11 - bank-width : Width in bytes of the device. Default is 1
12 - chip-delay : Chip dependent delay for transferring data from array to read
15 The device tree may optionally contain sub-nodes describing partitions of the
21 #address-cells = <1>;
22 #size-cells = <1>;
25 bank-width = <1>;
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| D | lpc32xx-slc.txt | 4 - compatible: "nxp,lpc3220-slc"
5 - reg: Address and size of the controller
6 - nand-on-flash-bbt: Use bad block table on flash
7 - gpios: GPIO specification for NAND write protect
11 - nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
12 - nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
15 - nxp,wwidth: Write pulse width (W_WIDTH)
16 - nxp,whold: Write hold time (W_HOLD)
17 - nxp,wsetup: Write setup time (W_SETUP)
18 - nxp,rwidth: Read pulse width (R_WIDTH)
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| D | cadence-nand-controller.txt | 4 - compatible : "cdns,hp-nfc"
5 - reg : Contains two entries, each of which is a tuple consisting of a
9 - reg-names: should contain "reg" and "sdma"
10 - #address-cells: should be 1. The cell encodes the chip select connection.
11 - #size-cells : should be 0.
12 - interrupts : The interrupt number.
13 - clocks: phandle of the controller core clock (nf_clk).
16 - dmas: shall reference DMA channel associated to the NAND controller
17 - cdns,board-delay-ps : Estimated Board delay. The value includes the total
18 round trip delay for the signals and is used for deciding on values
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| D | gpio-control-nand.txt | 4 read/write the NAND commands and data and GPIO pins for the control
8 - compatible : "gpio-control-nand"
9 - reg : should specify localbus chip select and size used for the chip. The
12 - #address-cells, #size-cells : Must be present if the device has sub-nodes
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
18 - bank-width : Width (in bytes) of the device. If not present, the width
20 - chip-delay : chip dependent delay for transferring data from array to
21 read registers (tR). If not present then a default of 20us is used.
22 - gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
26 read to ensure that the GPIO accesses have completed.
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| /Documentation/devicetree/bindings/net/nfc/ |
| D | ti,trf7970a.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Mark Greer <mgreer@animalcreek.com>
17 autosuspend-delay:
20 Specify autosuspend delay in milliseconds.
22 clock-frequency:
27 en2-rf-quirk:
35 irq-status-read-quirk:
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| /Documentation/accounting/ |
| D | taskstats-struct.rst | 13 2) Delay accounting fields
16 /* Delay accounting fields start */
20 /* Delay accounting fields end */
34 4) Per-task and per-thread context switch count statistics
38 6) Extended delay accounting fields for memory reclaim
69 /* The scheduling discipline as set in task->policy field. */
90 /* The minor page fault count of a task, as set in task->min_flt. */
93 /* The major page fault count of a task, as set in task->maj_flt. */
97 2) Delay accounting fields::
99 /* Delay accounting fields start
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| D | delay-accounting.rst | 2 Delay accounting
9 The per-task delay accounting functionality measures
18 g) write-protect copy
29 delay statistics aggregated for all tasks (or threads) belonging to a
34 aggregate delay statistics into arbitrary groups. To enable this, delay
40 ---------
42 Delay accounting uses the taskstats interface which is described
44 generic data structure to userspace corresponding to per-pid and per-tgid
45 statistics. The delay accounting functionality populates specific fields of
50 for a description of the fields pertaining to delay accounting.
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| /Documentation/sound/designs/ |
| D | timestamping.rst | 7 - Trigger_tstamp is the system time snapshot taken when the .trigger
11 estimate with a delay. In the latter two cases, the low-level driver
15 provides a refined estimate with a delay.
17 - tstamp is the current system timestamp updated during the last
19 The difference (tstamp - trigger_tstamp) defines the elapsed time.
22 and delay, which combined with the trigger and current system
29 - ``avail`` reports how much can be written in the ring buffer
30 - ``delay`` reports the time it will take to hear a new sample after all
33 When timestamps are enabled, the avail/delay information is reported
43 ascii-art, this could be represented as follows (for the playback
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| /Documentation/devicetree/bindings/net/ |
| D | motorcomm,yt8xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
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| /Documentation/timers/ |
| D | timekeeping.rst | 2 Clock sources, Clock events, sched_clock() and delay timers
10 If you grep through the kernel source you will find a number of architecture-
12 architecture-specific overrides of the sched_clock() function and some
13 delay timers.
17 on this timeline, providing facilities such as high-resolution timers.
18 sched_clock() is used for scheduling and timestamping, and delay timers
19 provide an accurate delay source using hardware counters.
23 -------------
27 a Linux system will eventually read the clock source to determine exactly
31 n bits which count from 0 to (2^n)-1 and then wraps around to 0 and start over.
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| /Documentation/filesystems/ |
| D | incfs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 Please update Documentation/ABI/testing/sysfs-fs-incfs if you update this
16 --------
18 /sys/fs/incremental-fs/features/corefs
21 /sys/fs/incremental-fs/features/v2
24 fs-verity support
35 /sys/fs/incremental-fs/features/zstd
38 /sys/fs/incremental-fs/features/bugfix_throttling
42 ------------------
47 /sys/fs/incremental-fs/instances/[name]
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