Searched full:ref_clk (Results 1 – 25 of 27) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ |
| D | cirrus,cs2000-cp.yaml | 25 Common clock binding for CLK_IN, XTI/REF_CLK
31 - const: ref_clk
44 - 0 # CS2000CP_AUX_OUTPUT_REF_CLK: ref_clk input
61 output signal directly from the REF_CLK input.
87 clock-names = "clk_in", "ref_clk";
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| D | baikal,bt1-ccu-div.yaml | 117 - const: ref_clk
183 clock-names = "ref_clk", "sata_clk", "pcie_clk",
194 clock-names = "ref_clk";
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| D | baikal,bt1-ccu-pll.yaml | 102 const: ref_clk
121 clock-names = "ref_clk";
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| /Documentation/devicetree/bindings/net/ |
| D | nxp,tja11xx.yaml | 52 The REF_CLK is provided for both transmitted and received data
56 connected to pin REF_CLK. A third option is to connect a 25MHz
57 clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
59 If present, indicates that the REF_CLK will be configured as
61 If not present, the REF_CLK will be configured as interface
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| D | xlnx,axi-ethernet.yaml | 107 - const: ref_clk
157 clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
182 clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
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| /Documentation/devicetree/bindings/phy/ |
| D | amlogic,g12a-usb3-pcie-phy.yaml | 26 - const: ref_clk
59 clocks = <&ref_clk>;
60 clock-names = "ref_clk";
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| D | samsung,ufs-phy.yaml | 78 - const: ref_clk
91 - const: ref_clk
109 clock-names = "ref_clk", "rx1_symbol_clk",
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| D | phy-cadence-torrent.yaml | 165 clocks = <&ref_clk>;
194 clocks = <&ref_clk>;
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| /Documentation/devicetree/bindings/i2c/ |
| D | apple,i2c.yaml | 44 Allowed values are between ref_clk/(16*4) and ref_clk/(16*255).
64 clocks = <&ref_clk>;
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| /Documentation/devicetree/bindings/usb/ |
| D | rockchip,dwc3.yaml | 67 - const: ref_clk
108 - const: ref_clk
133 - const: ref_clk
154 clock-names = "ref_clk", "suspend_clk",
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| D | rockchip,rk3399-dwc3.yaml | 42 - const: ref_clk
89 clock-names = "ref_clk", "suspend_clk",
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| D | dwc3-xilinx.yaml | 46 - const: ref_clk
117 clock-names = "bus_clk", "ref_clk";
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| /Documentation/devicetree/bindings/rtc/ |
| D | cdns,rtc.txt | 12 - ref_clk: reference 1Hz or 100Hz clock, depending on IP configuration
20 clock-names = "pclk", "ref_clk";
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| /Documentation/devicetree/bindings/spi/ |
| D | jcore,spi.txt | 15 - clocks: If a phandle named "ref_clk" is present, SPI clock speed
33 clock-names = "ref_clk";
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| D | xlnx,zynq-qspi.yaml | 37 - const: ref_clk
56 clock-names = "ref_clk", "pclk";
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| D | spi-zynqmp-qspi.yaml | 29 - const: ref_clk
60 clock-names = "ref_clk", "pclk";
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| D | spi-cadence.yaml | 29 - const: ref_clk
78 clock-names = "ref_clk", "pclk";
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| /Documentation/devicetree/bindings/ufs/ |
| D | qcom,ufs.yaml | 135 - const: ref_clk
169 - const: ref_clk
198 - const: ref_clk
230 - const: ref_clk
257 - const: ref_clk
332 "ref_clk",
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| D | renesas,ufs.yaml | 28 - const: ref_clk
57 clock-names = "fck", "ref_clk";
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| D | hisilicon,ufs.yaml | 43 - const: ref_clk
83 clock-names = "ref_clk", "phy_clk";
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| D | cdns,ufshc.yaml | 44 - const: ref_clk
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| /Documentation/devicetree/bindings/fpga/ |
| D | xilinx-zynq-fpga-mgr.yaml | 27 - const: ref_clk
50 clock-names = "ref_clk";
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| /Documentation/devicetree/bindings/clock/ti/davinci/ |
| D | pll.txt | 59 clocks = <&ref_clk>, <&pll1_sysclk 3>;
83 clocks = <&ref_clk>;
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| /Documentation/devicetree/bindings/iio/impedance-analyzer/ |
| D | adi,ad5933.yaml | 55 clocks = <&ref_clk>;
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | chipone,icn6211.yaml | 33 Optional external clock connected to REF_CLK input.
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