Searched full:refclk (Results 1 – 25 of 60) sorted by relevance
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | mediatek,mt7620-pinctrl.yaml | 39 pa, pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf,
40 refclk, rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlite,
41 wdt refclk, wdt rst, wled]
70 spi refclk, uartf, uartlite, wdt, wled]
138 const: pcie refclk
183 const: refclk
228 const: spi refclk
232 enum: [spi refclk]
255 const: wdt refclk
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| D | mediatek,mt7621-pinctrl.yaml | 38 enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk,
40 uart1, uart2, uart3, wdt refclk, wdt rst]
119 const: pcie refclk
227 const: wdt refclk
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| /Documentation/devicetree/bindings/usb/ |
| D | octeon-usb.txt | 24 - cavium,refclk-type: type of the USB reference clock. Allowed values are
27 - refclk-frequency: deprecated, use "clock-frequency".
29 - refclk-type: deprecated, use "cavium,refclk-type".
54 cavium,refclk-type = "crystal";
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| D | smsc,usb3503.yaml | 64 Clock used for driving REFCLK signal. If not provided the driver assumes
70 const: refclk
72 refclk-frequency:
75 Frequency of the REFCLK signal as defined by REF_SEL pins. If not
76 provided, driver will not set rate of the REFCLK signal and assume that a
122 clock-names = "refclk";
141 clock-names = "refclk";
156 refclk-frequency = <19200000>;
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| D | dwc3-cavium.txt | 18 refclk-frequency = <0x05f5e100>;
19 refclk-type-ss = "dlmc_ref_clk0";
20 refclk-type-hs = "dlmc_ref_clk0";
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| D | ti,am62-usb.yaml | 45 ti,syscon-phy-pll-refclk:
72 - ti,syscon-phy-pll-refclk
92 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | uctl.txt | 16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
30 refclk-frequency = <24000000>;
32 refclk-type = "crystal";
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| /Documentation/devicetree/bindings/phy/ |
| D | fsl,imx8-pcie-phy.yaml | 43 fsl,refclk-pad-mode:
45 Specifies the mode of the refclk pad used. It can be UNUSED(PHY
47 is provided externally via the refclk pad) or OUTPUT(PHY refclock
48 is derived from SoC internal source and provided on the refclk pad).
79 - fsl,refclk-pad-mode
99 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
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| D | ti,phy-j721e-wiz.yaml | 74 refclk-dig:
113 "^pll[0|1]-refclk$":
216 pll0-refclk {
223 pll1-refclk {
230 cmn-refclk-dig-div {
240 refclk-dig {
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| D | fsl,imx8qm-hsio.yaml | 67 fsl,refclk-pad-mode:
69 Specifies the mode of the refclk pad used. INPUT(PHY refclock is
70 provided externally via the refclk pad) or OUTPUT(PHY refclock is
71 derived from SoC internal source and provided on the refclk pad).
162 fsl,refclk-pad-mode = "input";
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| D | rockchip-pcie-phy.txt | 8 - clock-names: Must be "refclk"
32 clock-names = "refclk";
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| D | phy-cadence-torrent.yaml | 39 PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
42 Same refclk is used for both PLL0 and PLL1 if no separate pll1_refclk is used.
49 - const: refclk
166 clock-names = "refclk";
195 clock-names = "refclk";
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| D | pistachio-usb-phy.txt | 12 - img,refclk: Indicates the reference clock source for the USB PHY.
26 img,refclk = <REFCLK_CLK_CORE>;
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| D | ti,omap-usb2.yaml | 44 - const: refclk
78 clock-names = "wkupclk", "refclk";
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| D | ti-phy.txt | 45 * "refclk" - reference clock.
84 "refclk";
95 clock-names = "sysclk", "refclk";
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| /Documentation/devicetree/bindings/clock/ |
| D | marvell,berlin.txt | 18 "refclk" for the SoCs oscillator input on all SoCs,
29 clocks = <&refclk>;
30 clock-names = "refclk";
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| D | ti,am62-audio-refclk.yaml | 4 $id: http://devicetree.org/schemas/clock/ti,am62-audio-refclk.yaml#
15 - const: ti,am62-audio-refclk
37 compatible = "ti,am62-audio-refclk";
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| D | nuvoton,npcm750-clk.txt | 36 clock-names = "refclk", "sysbypck", "mcbypck";
43 clk_refclk: clk-refclk {
47 clock-output-names = "refclk";
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| /Documentation/devicetree/bindings/serial/ |
| D | brcm,bcm6345-uart.yaml | 29 const: refclk
46 clock-names = "refclk";
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | toshiba,tc358746.yaml | 31 hardware pin REFCLK.
35 const: refclk
141 clocks = <&refclk>;
142 clock-names = "refclk";
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| D | tc358743.txt | 10 source, the clock input is named "refclk".
34 clock-names = "refclk";
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| /Documentation/devicetree/bindings/sound/ |
| D | amlogic,axg-spdifin.yaml | 36 - const: refclk
85 clock-names = "pclk", "refclk";
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| /Documentation/devicetree/bindings/watchdog/ |
| D | marvell,cn10624-wdt.yaml | 45 - const: refclk
78 clock-names = "refclk";
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| /Documentation/devicetree/bindings/arm/ |
| D | sp810.yaml | 35 - const: refclk
72 clock-names = "refclk", "timclk", "apb_pclk";
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| /Documentation/devicetree/bindings/pci/ |
| D | nvidia,tegra194-pcie-ep.yaml | 165 nvidia,refclk-select-gpios:
167 description: GPIO used to enable REFCLK to controller from the host
169 nvidia,enable-ext-refclk:
250 nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
297 nvidia,enable-ext-refclk;
306 nvidia,refclk-select-gpios = <&gpio_aon
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