Searched +full:reset +full:- +full:names (Results 1 – 25 of 766) sorted by relevance
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| /Documentation/devicetree/bindings/reset/ |
| D | socionext,uniphier-glue-reset.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier peripheral core reset in glue layer
10 Some peripheral core reset belongs to its own glue layer. Before using
11 this core reset, it is necessary to control the clocks and resets to
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-reset
22 - socionext,uniphier-pro5-usb3-reset
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| D | reset.txt | 1 = Reset Signal Device Tree Bindings =
3 This binding is intended to represent the hardware reset signals present
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
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| D | nxp,lpc1850-rgu.txt | 1 NXP LPC1850 Reset Generation Unit (RGU)
4 Please also refer to reset.txt in this directory for common reset
8 - compatible: Should be "nxp,lpc1850-rgu"
9 - reg: register base and length
10 - clocks: phandle and clock specifier to RGU clocks
11 - clock-names: should contain "delay" and "reg"
12 - #reset-cells: should be 1
14 See table below for valid peripheral reset numbers. Numbers not
18 Reset Peripheral
20 12 ARM Cortex-M0 subsystem core (LPC43xx only)
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| D | microchip,rst.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/microchip,rst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 Switch Reset Controller
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The Microchip Sparx5 Switch provides reset control and implements the following
16 - One Time Switch Core Reset (Soft Reset)
20 pattern: "^reset-controller@[0-9a-f]+$"
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| /Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
20 - enum:
21 - qcom,pcie-apq8064
22 - qcom,pcie-apq8084
23 - qcom,pcie-ipq4019
24 - qcom,pcie-ipq6018
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| D | hisilicon-histb-pcie.txt | 6 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
11 - compatible: Should be one of the following strings:
12 "hisilicon,hi3798cv200-pcie"
13 - reg: Should contain sysctl, rc_dbi, config registers location and length.
14 - reg-names: Must include the following entries:
16 "rc-dbi": configuration space of PCIe controller;
18 - bus-range: PCI bus numbers covered.
19 - interrupts: MSI interrupt.
20 - interrupt-names: Must include "msi" entries.
21 - clocks: List of phandle and clock specifier pairs as listed in clock-names
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| /Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-gr3d.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr3d.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^gr3d@[0-9a-f]+$"
19 - nvidia,tegra20-gr3d
20 - nvidia,tegra30-gr3d
21 - nvidia,tegra114-gr3d
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| D | nvidia,tegra186-display.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^display-hub@[0-9a-f]+$"
19 - nvidia,tegra186-display
20 - nvidia,tegra194-display
22 '#address-cells':
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| D | nvidia,tegra20-host1x.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The host1x top-level node defines a number of children, each
19 - enum:
20 - nvidia,tegra20-host1x
21 - nvidia,tegra30-host1x
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| /Documentation/devicetree/bindings/sound/ |
| D | mt8183-afe-pcm.txt | 4 - compatible = "mediatek,mt68183-audio";
5 - reg: register location and size
6 - interrupts: should contain AFE interrupt
7 - resets: Must contain an entry for each entry in reset-names
8 See ../reset/reset.txt for details.
9 - reset-names: should have these reset names:
11 - power-domains: should define the power domain
12 - clocks: Must contain an entry for each entry in clock-names
13 - clock-names: should have these clock names:
23 afe: mt8183-afe-pcm@11220000 {
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| D | img,parallel-out.txt | 5 - compatible : Compatible list, must contain "img,parallel-out".
7 - #sound-dai-cells : Must be equal to 0
9 - reg : Offset and length of the register set for the device.
11 - dmas: Contains an entry for each entry in dma-names.
13 - dma-names: Must include the following entry:
16 - clocks : Contains an entry for each entry in clock-names.
18 - clock-names : Includes the following entries:
22 - resets: Contains a phandle to the parallel out reset signal
24 - reset-names: Contains the reset signal name "rst"
28 - interrupts : Contains the parallel out interrupt, if present
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| /Documentation/devicetree/bindings/usb/ |
| D | dwc3-xilinx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mubin Sayyed <mubin.sayyed@amd.com>
11 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
16 - enum:
17 - xlnx,zynqmp-dwc3
18 - xlnx,versal-dwc3
22 "#address-cells":
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| D | ehci-st.txt | 4 - compatible : must be "st,st-ehci-300x"
5 - reg : physical base addresses of the controller and length of memory mapped
7 - interrupts : one EHCI interrupt should be described here
8 - pinctrl-names : a pinctrl state named "default" must be defined
9 - pinctrl-0 : phandle referencing pin configuration of the USB controller
10 See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
11 - clocks : phandle list of usb clocks
12 - clock-names : should be "ic" for interconnect clock and "clk48"
13 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - phys : phandle for the PHY device
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| D | ohci-st.txt | 5 - compatible : must be "st,st-ohci-300x"
6 - reg : physical base addresses of the controller and length of memory mapped
8 - interrupts : one OHCI controller interrupt should be described here
9 - clocks : phandle list of usb clocks
10 - clock-names : should be "ic" for interconnect clock and "clk48"
11 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
13 - phys : phandle for the PHY device
14 - phy-names : should be "usb"
16 - resets : phandle to the powerdown and reset controller for the USB IP
17 - reset-names : should be "power" and "softreset".
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| D | hisilicon,histb-xhci.txt | 6 - compatible: should be "hisilicon,hi3798cv200-xhci"
7 - reg: specifies physical base address and size of the registers
8 - interrupts : interrupt used by the controller
9 - clocks: a list of phandle + clock-specifier pairs, one for each
10 entry in clock-names
11 - clock-names: must contain
16 - resets: a list of phandle and reset specifier pairs as listed in
17 reset-names property.
18 - reset-names: must contain
19 "soft": for soft reset
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| /Documentation/devicetree/bindings/phy/ |
| D | allwinner,sun9i-a80-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun9i-a80-usb-phy
25 - maxItems: 1
28 - items:
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| D | rockchip,rk3588-hdptx-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
15 - rockchip,rk3588-hdptx-phy
22 - description: Reference clock
23 - description: APB clock
25 clock-names:
27 - const: ref
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| D | rockchip-pcie-phy.txt | 2 -----------------------
5 - compatible: rockchip,rk3399-pcie-phy
6 - clocks: Must contain an entry in clock-names.
7 See ../clocks/clock-bindings.txt for details.
8 - clock-names: Must be "refclk"
9 - resets: Must contain an entry in reset-names.
10 See ../reset/reset.txt for details.
11 - reset-names: Must be "phy"
14 - #phy-cells: must be 0
16 Required properties for per-lane PHY mode (preferred):
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| D | socionext,uniphier-ahci-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-ahci-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - socionext,uniphier-pro4-ahci-phy
20 - socionext,uniphier-pxs2-ahci-phy
21 - socionext,uniphier-pxs3-ahci-phy
26 "#phy-cells":
33 clock-names:
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| /Documentation/devicetree/bindings/power/ |
| D | amlogic,meson-ee-pwrc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/power/amlogic,meson-ee-pwrc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson Everything-Else Power Domains
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Everything-Else Power Domains node should be the child of a syscon
17 - compatible: Should be the following:
18 "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"
26 - amlogic,meson8-pwrc
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| /Documentation/devicetree/bindings/gpu/ |
| D | nvidia,gk20a.txt | 4 - compatible: "nvidia,<gpu>"
6 - nvidia,gk20a
7 - nvidia,gm20b
8 - nvidia,gp10b
9 - nvidia,gv11b
10 - reg: Physical base address and length of the controller's registers.
12 - first entry for bar0
13 - second entry for bar1
14 - interrupts: Must contain an entry for each entry in interrupt-names.
15 See ../interrupt-controller/interrupts.txt for details.
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| /Documentation/devicetree/bindings/crypto/ |
| D | rockchip,rk3288-crypto.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/rockchip,rk3288-crypto.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3288-crypto
16 - rockchip,rk3328-crypto
17 - rockchip,rk3399-crypto
29 clock-names:
37 reset-names:
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| /Documentation/devicetree/bindings/dma/ |
| D | qcom,adm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
27 "#dma-cells":
32 - description: phandle to the core clock
33 - description: phandle to the iface clock
35 clock-names:
37 - const: core
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| /Documentation/devicetree/bindings/soc/socionext/ |
| D | socionext,uniphier-dwc3-glue.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
20 - enum:
21 - socionext,uniphier-pro4-dwc3-glue
22 - socionext,uniphier-pro5-dwc3-glue
23 - socionext,uniphier-pxs2-dwc3-glue
24 - socionext,uniphier-ld20-dwc3-glue
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| /Documentation/devicetree/bindings/ata/ |
| D | ahci-st.txt | 6 - compatible : Must be "st,ahci"
7 - reg : Physical base addresses and length of register sets
8 - interrupts : Interrupt associated with the SATA device
9 - interrupt-names : Associated name must be; "hostc"
10 - clocks : The phandle for the clock
11 - clock-names : Associated name must be; "ahci_clk"
12 - phys : The phandle for the PHY port
13 - phy-names : Associated name must be; "ahci_phy"
16 - resets : The power-down, soft-reset and power-reset lines of SATA IP
17 - reset-names : Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst"
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