Searched full:resets (Results 1 – 25 of 851) sorted by relevance
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| /Documentation/devicetree/bindings/regulator/ |
| D | socionext,uniphier-regulator.yaml | 11 the regulator, it is necessary to control the clocks and resets to enable
12 this layer. These clocks and resets should be described in each property.
38 resets:
62 resets:
75 resets:
87 - resets
98 resets = <&sys_rst 14>;
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| /Documentation/devicetree/bindings/reset/ |
| D | socionext,uniphier-glue-reset.yaml | 11 this core reset, it is necessary to control the clocks and resets to
12 enable this layer. These clocks and resets should be described in each
45 resets:
71 resets:
84 resets:
97 - resets
109 resets = <&sys_rst 14>;
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-hisi-inno-usb2.txt | 11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
23 - resets: The phandle and reset specifier pair for PHY port reset signal.
40 resets = <&crg 0xbc 4>;
47 resets = <&crg 0xbc 8>;
53 resets = <&crg 0xbc 9>;
61 resets = <&crg 0xbc 6>;
68 resets = <&crg 0xbc 10>;
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| D | socionext,uniphier-ahci-phy.yaml | 37 resets:
60 resets:
82 resets:
103 resets:
117 - resets
131 resets = <&sys_rst 28>, <&sys_rst 30>;
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| D | qcom,msm8996-qmp-pcie-phy.yaml | 41 resets:
79 resets:
103 - resets
118 - resets
140 resets = <&gcc GCC_PCIE_PHY_BCR>,
154 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
168 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
182 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
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| D | phy-cadence-sierra.yaml | 32 resets:
85 resets:
89 Contains list of resets, one per lane, to get all the link lanes out of reset.
119 - resets
129 - resets
145 resets = <&phyrst 0>, <&phyrst 1>;
153 resets = <&phyrst 2>;
160 resets = <&phyrst 4>;
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| D | socionext,uniphier-pcie-phy.yaml | 38 resets:
65 resets:
78 resets:
89 - resets
103 resets = <&sys_rst 24>;
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| D | phy-cadence-torrent.yaml | 64 resets:
88 resets:
92 Contains list of resets, one per lane, to get all the link lanes out of reset.
130 - resets
145 - resets
163 resets = <&phyrst 0>;
171 resets = <&phyrst 1>, <&phyrst 2>,
192 resets = <&phyrst 0>, <&phyrst 1>;
200 resets = <&phyrst 2>, <&phyrst 3>;
209 resets = <&phyrst 4>;
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| D | socionext,uniphier-usb3ss-phy.yaml | 42 resets:
68 resets:
91 resets:
116 resets:
130 - resets
144 resets = <&sys_rst 14>, <&sys_rst 16>;
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| D | st,stih407-usb2-phy.yaml | 30 resets:
46 - resets
54 #include <dt-bindings/reset/stih407-resets.h>
59 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
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| D | allwinner,sun9i-a80-usb-phy.yaml | 42 resets:
69 - resets
90 resets:
106 resets = <&usb_clocks RST_USB0_PHY>;
125 resets = <&usb_clocks RST_USB2_PHY>,
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| D | qcom,usb-hs-phy.yaml | 22 resets:
30 resets:
62 resets: true
91 - resets
108 resets = <&gcc 10>, <&otg 0>;
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| /Documentation/devicetree/bindings/crypto/ |
| D | rockchip,rk3288-crypto.yaml | 33 resets:
57 resets:
76 resets:
95 resets:
109 - resets
125 resets = <&cru SRST_CRYPTO>;
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| /Documentation/devicetree/bindings/display/ |
| D | renesas,du.yaml | 53 resets: true
128 resets:
178 resets:
202 - resets
233 resets:
256 - resets
286 resets:
310 - resets
340 resets:
366 - resets
[all …]
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| D | st,stih4xx.txt | 38 - resets: resets to be used by the device
40 - reset-names: names of the resets listed in resets property in the same
51 - resets: resets to be used by the device
53 - reset-names: names of the resets listed in resets property in the same
111 - resets: resets to be used by the device
113 - reset-names: names of the resets listed in resets property in the same
187 resets = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
196 resets = <&softreset STIH416_HDTVOUT_SOFTRESET>;
236 resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
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| /Documentation/devicetree/bindings/watchdog/ |
| D | starfive,jh7100-wdt.yaml | 49 resets:
58 - resets
71 resets:
76 resets:
91 resets = <&rst 99>,
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| /Documentation/devicetree/bindings/sound/ |
| D | snps,designware-i2s.yaml | 60 resets:
62 - description: Optional controller resets
115 resets:
119 resets:
136 - resets
151 - resets
166 - resets
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| D | amlogic,axg-fifo.yaml | 42 resets:
60 - resets
77 resets:
88 resets:
109 resets = <&arb>, <&clkc_audio AUD_RESET_FRDDR_A>;
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| /Documentation/devicetree/bindings/media/cec/ |
| D | st,stih-cec.yaml | 33 resets:
44 - resets
52 #include <dt-bindings/reset/stih407-resets.h>
65 resets = <&softreset STIH407_LPM_SOFTRESET>;
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| /Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-host1x.yaml | 70 resets:
136 - resets
157 resets:
257 resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
270 resets = <&tegra_car 60>;
279 resets = <&tegra_car 100>;
288 resets = <&tegra_car 19>;
297 resets = <&tegra_car 23>;
306 resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
314 resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
[all …]
|
| /Documentation/devicetree/bindings/nvmem/ |
| D | rockchip,otp.yaml | 34 resets:
47 - resets
65 resets:
81 resets:
105 resets = <&cru SRST_OTP_PHY>;
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| /Documentation/devicetree/bindings/ata/ |
| D | nvidia,tegra-ahci.yaml | 46 resets:
94 - resets
110 resets:
131 resets:
146 resets:
171 resets = <&tegra_car 124>,
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| /Documentation/devicetree/bindings/usb/ |
| D | dwc3-xilinx.yaml | 48 resets:
50 A list of phandles for resets listed in reset-names.
94 - resets
103 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
105 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
119 resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
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| /Documentation/devicetree/bindings/net/ |
| D | socionext,uniphier-ave4.yaml | 48 resets:
88 resets:
101 resets:
114 - resets
131 resets = <&sys_rst 6>;
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| /Documentation/devicetree/bindings/pci/ |
| D | socionext,uniphier-pcie-ep.yaml | 45 resets:
86 resets:
102 resets:
113 - resets
128 resets = <&sys_rst 12>, <&sys_rst 24>;
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