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/Documentation/devicetree/bindings/net/
Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/net/adi,adin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
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Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/motorcomm,yt8xxx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
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Dxlnx,gmii-to-rgmii.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,gmii-to-rgmii.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx GMII to RGMII Converter
10 - Harini Katakam <harini.katakam@amd.com>
14 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
24 const: xlnx,gmii-to-rgmii-1.0
29 description: The ID number for the phy.
31 phy-handle:
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Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
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Damlogic,meson-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
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Dqcom,ethqos.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,ethqos.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
17 - $ref: snps,dwmac.yaml#
22 - qcom,qcs404-ethqos
23 - qcom,sa8775p-ethqos
24 - qcom,sc8280xp-ethqos
25 - qcom,sm8150-ethqos
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Dengleder,tsnep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/engleder,tsnep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gerhard Engleder <gerhard@engleder-embedded.com>
13 - $ref: ethernet-controller.yaml#
26 interrupt-names:
29 - const: mac
30 - const: txrx-1
31 - const: txrx-2
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Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/ti,dp83867.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
25 Media Independent Interface (GMII) or Reduced GMII (RGMII).
34 nvmem-cells:
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Dapm-xgene-enet.txt1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
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Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/net/qca,ar803x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
26 qca,clk-out-strength:
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Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
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Dapm-xgene-mdio.txt1 APM X-Gene SoC MDIO node
3 MDIO node is defined to describe on-chip MDIO controller.
6 - compatible: Must be "apm,xgene-mdio-rgmii" or "apm,xgene-mdio-xfi"
7 - #address-cells: Must be <1>.
8 - #size-cells: Must be <0>.
9 - reg: Address and length of the register set
10 - clocks: Reference to the clock entry
13 - compatible: PHY identifier. Please refer ./phy.txt for the format.
14 - reg: The ID number for the phy.
19 compatible = "apm,xgene-mdio-rgmii";
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Dti,icssg-prueth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,icssg-prueth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Md Danish Anwar <danishanwar@ti.com>
13 Ethernet based on the Programmable Real-Time Unit and Industrial
19 - ti,am642-icssg-prueth # for AM64x SoC family
20 - ti,am654-icssg-prueth # for AM65x SoC family
21 - ti,am654-sr1-icssg-prueth # for AM65x SoC family, SR1.0
32 dma-names:
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Drenesas,ethertsn.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,ethertsn.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Ethernet TSN End-station
10 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
17 - $ref: ethernet-controller.yaml#
22 - enum:
23 - renesas,r8a779g0-ethertsn # R-Car V4H
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Dingenic,mac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ingenic,mac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
18 - ingenic,jz4775-mac
19 - ingenic,x1000-mac
20 - ingenic,x1600-mac
21 - ingenic,x1830-mac
22 - ingenic,x2000-mac
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/Documentation/devicetree/bindings/net/dsa/
Dnxp,sja1105.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
16 - Vladimir Oltean <vladimir.oltean@nxp.com>
21 - nxp,sja1105e
22 - nxp,sja1105t
23 - nxp,sja1105p
24 - nxp,sja1105q
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Darrow,xrs700x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/arrow,xrs700x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: dsa.yaml#/$defs/ethernet-ports
13 - George McCollister <george.mccollister@gmail.com>
18 RGMII ports and one RMII port and are managed via i2c or mdio.
23 - enum:
24 - arrow,xrs7003e
25 - arrow,xrs7003f
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Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/microchip,lan937x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - UNGLinuxDriver@microchip.com
13 - $ref: dsa.yaml#/$defs/ethernet-ports
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
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Dbrcm,sf2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/brcm,sf2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
15 - enum:
16 - brcm,bcm4908-switch
17 - brcm,bcm7278-switch-v4.0
18 - brcm,bcm7278-switch-v4.8
19 - brcm,bcm7445-switch-v4.0
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/Documentation/ABI/testing/
Dsysfs-class-net-phydev24 This attribute contains the 32-bit PHY Identifier as reported
26 This ID is used to match the device with the appropriate
41 <empty> (not available), mii, gmii, sgmii, tbi, rev-mii,
42 rmii, rgmii, rgmii-id, rgmii-rxid, rgmii-txid, rtbi, smii
43 xgmii, moca, qsgmii, trgmii, 1000base-x, 2500base-x, rxaui,
44 xaui, 10gbase-kr, unknown
60 32-bit hexadecimal number representing a bit mask of the
/Documentation/devicetree/bindings/clock/
Dstarfive,jh7110-aoncrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Always-On Clock and Reset Generator
10 - Emil Renner Berthing <kernel@esmil.dk>
14 const: starfive,jh7110-aoncrg
21 - items:
22 - description: Main Oscillator (24 MHz)
23 - description: GMAC0 RMII reference or GMAC0 RGMII RX
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/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
Ducc.txt4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
20 driver should use "Soft-UART" mode, which is needed on some SOCs that have
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/Documentation/devicetree/bindings/pinctrl/
Dralink,rt305x-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/ralink,rt305x-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,rt305x-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
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Dralink,rt3352-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/ralink,rt3352-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,rt3352-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
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/Documentation/devicetree/bindings/phy/
Dmicrochip,lan966x-serdes.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/microchip,lan966x-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
14 3 SERDES6G and 2 RGMII interfaces. Two of the SERDES6G support QSGMII.
20 following macros are defined CU(X), SERDES6G(X), RGMII(X). Where X is a
27 pattern: "^serdes@[0-9a-f]+$"
30 const: microchip,lan966x-serdes
34 - description: HSIO registers
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