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/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
[all …]
Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
[all …]
/Documentation/devicetree/bindings/media/
Dst-rc.txt1 Device-Tree bindings for ST IRB IP
4 - compatible: Should contain "st,comms-irb".
5 - reg: Base physical address of the controller and length of memory
7 - interrupts: interrupt-specifier for the sole interrupt generated by
10 - rx-mode: can be "infrared" or "uhf". This property specifies the L1
11 protocol used for receiving remote control signals. rx-mode should
12 be present iff the rx pins are wired up.
13 - tx-mode: should be "infrared". This property specifies the L1
14 protocol used for transmitting remote control signals. tx-mode should
15 be present iff the tx pins are wired up.
[all …]
/Documentation/devicetree/bindings/serial/
Dst,stm32-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Erwan Le Ray <erwan.leray@foss.st.com>
15 - st,stm32-uart
16 - st,stm32f7-uart
17 - st,stm32h7-uart
34 st,hw-flow-ctrl:
38 rx-tx-swap: true
[all …]
Dpl011.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
13 - $ref: /schemas/arm/primecell.yaml#
14 - $ref: serial.yaml#
22 - arm,pl011
24 - compatible
29 - const: arm,pl011
30 - const: arm,primecell
[all …]
Dserial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
19 where N is the port number (non-negative decimal integer) as printed on the
28 cts-gpios:
34 dcd-gpios:
40 dsr-gpios:
46 dtr-gpios:
[all …]
/Documentation/devicetree/bindings/net/
Dlantiq,pef2256.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
20 - const: lantiq,pef2256
27 - description: Master Clock
28 - description: System Clock Receive
29 - description: System Clock Transmit
31 clock-names:
33 - const: mclk
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dcirrus,lochnagar.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of various
26 [2] Pinctrl: ../pinctrl/pinctrl-bindings.txt
29 [3] include/dt-bindings/pinctrl/lochnagar.h
37 - cirrus,lochnagar-pinctrl
39 gpio-controller: true
41 '#gpio-cells':
[all …]
Dmicrochip,pic32-pinctrl.txt3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
7 PIC32 'pin configuration node' is a node of a group of pins which can be
9 pins, optional function, and optional mux related configuration.
12 - compatible: "microchip,pic32mada-pinctrl"
13 - reg: Address range of the pinctrl registers.
14 - clocks: Clock specifier (see clock bindings for details)
16 Required properties for pin configuration sub-nodes:
17 - pins: List of pins to which the configuration applies.
19 Optional properties for pin configuration sub-nodes:
[all …]
Dqcom,ipq8064-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq8064-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,ipq8064-pinctrl
28 gpio-reserved-ranges: true
31 "-state$":
33 - $ref: "#/$defs/qcom-ipq8064-tlmm-state"
[all …]
Dqcom,apq8064-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,apq8064-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,apq8064-pinctrl
28 gpio-reserved-ranges: true
31 "-state$":
33 - $ref: "#/$defs/qcom-apq8064-tlmm-state"
[all …]
Dsunplus,sp7021-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Dvorkin Dmitry <dvorkin@tibbo.com>
12 - Wells Lu <wellslutw@gmail.com>
15 The Sunplus SP7021 pin controller is used to control SoC pins. Please
16 refer to pinctrl-bindings.txt in this directory for details of the common
19 SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All
20 are multiplexed with some special function pins. SP7021 has 3 types of
[all …]
Dbrcm,ns2-pinmux.txt4 are some individual pins that support modifying the pinconf parameters.
8 - compatible:
9 Must be "brcm,ns2-pinmux"
11 - reg:
17 - function:
20 - groups:
23 - pins:
26 The generic properties bias-disable, bias-pull-down, bias-pull-up,
27 drive-strength, slew-rate, input-enable, input-disable are supported
28 for some individual pins listed at the end.
[all …]
Dqcom,sm4450-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm4450-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tengfei Fan <quic_tengfan@quicinc.com>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,sm4450-tlmm
26 interrupt-controller: true
27 "#interrupt-cells": true
28 gpio-controller: true
[all …]
Dstarfive,jh7100-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
12 Out of the SoC's many pins only the ones named PAD_GPIO[0] to PAD_GPIO[63]
15 interesting 2-layered approach to pin muxing best illustrated by the diagram
21 LCD output -----------------| |
22 CMOS Camera interface ------| |--- PAD_GPIO[0]
23 Ethernet PHY interface -----| MUX |--- PAD_GPIO[1]
[all …]
Dqcom,ipq5018-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq5018-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
18 const: qcom,ipq5018-tlmm
26 gpio-reserved-ranges:
30 gpio-line-names:
34 "-state$":
[all …]
Dqcom,sdx75-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdx75-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rohit Agarwal <quic_rohiagar@quicinc.com>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,sdx75-tlmm
28 gpio-reserved-ranges:
32 gpio-line-names:
36 "-state$":
[all …]
Dqcom,msm8909-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8909-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephan Gerhold <stephan@gerhold.net>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,msm8909-tlmm
28 gpio-reserved-ranges: true
31 "-state$":
33 - $ref: "#/$defs/qcom-msm8909-tlmm-state"
[all …]
Dqcom,apq8084-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,apq8084-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,apq8084-pinctrl
28 gpio-reserved-ranges: true
31 "-state$":
33 - $ref: "#/$defs/qcom-apq8084-tlmm-state"
[all …]
Dqcom,sm7150-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm7150-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Danila Tikhonov <danila@jiaxyga.com>
17 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
21 const: qcom,sm7150-tlmm
26 reg-names:
28 - const: west
[all …]
Dqcom,sc8180x-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,sc8180x-tlmm
25 reg-names:
27 - const: west
28 - const: east
[all …]
/Documentation/devicetree/bindings/spi/
Dmicrochip,spi-pic32.txt4 - compatible: Should be "microchip,pic32mzda-spi".
5 - reg: Address and length of register space for the device.
6 - interrupts: Should contain all three spi interrupts in sequence
7 of <fault-irq>, <receive-irq>, <transmit-irq>.
8 - interrupt-names: Should be "fault", "rx", "tx" in order.
9 - clocks: Phandle of the clock generating SPI clock on the bus.
10 - clock-names: Should be "mck0".
11 - cs-gpios: Specifies the gpio pins to be used for chipselects.
12 See: Documentation/devicetree/bindings/spi/spi-bus.txt
15 - dmas: Two or more DMA channel specifiers following the convention outlined
[all …]
Dspi-rockchip.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-rockchip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - $ref: spi-controller.yaml#
17 - Heiko Stuebner <heiko@sntech.de>
23 - const: rockchip,rk3036-spi
24 - const: rockchip,rk3066-spi
25 - const: rockchip,rk3228-spi
26 - const: rockchip,rv1108-spi
[all …]
/Documentation/devicetree/bindings/firmware/
Darm,scmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <sudeep.holla@arm.com>
26 - $ref: /schemas/firmware/nxp,imx95-scmi.yaml
34 - description: SCMI compliant firmware with mailbox transport
36 - const: arm,scmi
37 - description: SCMI compliant firmware with ARM SMC/HVC transport
39 - const: arm,scmi-smc
40 - description: SCMI compliant firmware with ARM SMC/HVC transport
[all …]
/Documentation/devicetree/bindings/sound/
Dmicrochip,sama7g5-i2smcc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/microchip,sama7g5-i2smcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip I2S Multi-Channel Controller
10 - Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
13 The I2SMCC complies with the Inter-IC Sound (I2S) bus specification and
15 multi-channel audio codecs. It consists of a receiver, a transmitter and a
19 multi-channel is supported by using multiple data pins, output and
23 "#sound-dai-cells":
[all …]

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