| /Documentation/networking/net_cachelines/ |
| D | tcp_sock.rst | 11 …ostly read_mostly tcp_bound_to_half_wnd,tcp_current_mss(tx);tcp_rcv_established(rx)
13 … read_write read_mostly tcp_select_window(tx);tcp_rcv_established(rx)
14 … bytes_received - read_write tcp_rcv_nxt_update(rx)
15 … segs_in - read_write tcp_v6_rcv(rx)
16 … data_segs_in - read_write tcp_v6_rcv(rx)
17 …);tcp_v6_do_rcv,tcp_rcv_established,tcp_data_queue,tcp_receive_window,tcp_rcv_nxt_update(write)(rx)
20 …transmit_skb,tcp_event_new_data_sent(write)(tx);tcp_rcv_established,tcp_ack,tcp_clean_rtx_queue(rx)
26 …k,tcp_cwnd_validate(tx);tcp_ack,tcp_may_update_window,tcp_clean_rtx_queue(write),tcp_ack_tstamp(rx)
32 … read_mostly read_mostly tcp_established_options(tx);tcp_fast_parse_options(rx)
36 … read_mostly read_mostly tcp_wnd_end,tcp_tso_should_defer(tx);tcp_fast_path_on(rx)
[all …]
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| /Documentation/virt/kvm/ |
| D | ppc-pv.rst | 84 ld rX, -4096(0)
153 mfmsr rX ld rX, magic_page->msr
154 mfsprg rX, 0 ld rX, magic_page->sprg0
155 mfsprg rX, 1 ld rX, magic_page->sprg1
156 mfsprg rX, 2 ld rX, magic_page->sprg2
157 mfsprg rX, 3 ld rX, magic_page->sprg3
158 mfsrr0 rX ld rX, magic_page->srr0
159 mfsrr1 rX ld rX, magic_page->srr1
160 mfdar rX ld rX, magic_page->dar
161 mfdsisr rX lwz rX, magic_page->dsisr
[all …]
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| /Documentation/devicetree/bindings/sound/ |
| D | qcom,lpass-rx-macro.yaml | 4 $id: http://devicetree.org/schemas/sound/qcom,lpass-rx-macro.yaml#
7 title: LPASS(Low Power Audio Subsystem) RX Macro audio codec
16 - qcom,sc7280-lpass-rx-macro
17 - qcom,sm8250-lpass-rx-macro
18 - qcom,sm8450-lpass-rx-macro
19 - qcom,sm8550-lpass-rx-macro
20 - qcom,sc8280xp-lpass-rx-macro
23 - qcom,sm8650-lpass-rx-macro
24 - qcom,x1e80100-lpass-rx-macro
25 - const: qcom,sm8550-lpass-rx-macro
[all …]
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| D | qcom,wcd937x-sdw.yaml | 14 It has RX and TX Soundwire slave devices. This bindings is for the
42 qcom,rx-port-mapping:
44 Specifies static port mapping between device and host rx ports.
47 Supports maximum 5 rx soundwire ports.
49 WCD9370 RX Port 1 (HPH_L/R) <==> SWR1 Port 1 (HPH_L/R)
50 WCD9370 RX Port 2 (CLSH) <==> SWR1 Port 2 (CLSH)
51 WCD9370 RX Port 3 (COMP_L/R) <==> SWR1 Port 3 (COMP_L/R)
52 WCD9370 RX Port 4 (LO) <==> SWR1 Port 4 (LO)
53 WCD9370 RX Port 5 (DSD_L/R) <==> SWR1 Port 5 (DSD)
76 qcom,rx-port-mapping = <1 2 3 4 5>;
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| D | rockchip,i2s-tdm.yaml | 45 - rx
52 - description: clock for RX
79 description: resets for the tx and rx directions
87 - rx-m
103 description: Use TX BCLK/LRCK for both TX and RX.
105 rockchip,trcm-sync-rx-only:
107 description: Use RX BCLK/LRCK for both TX and RX.
112 rockchip,i2s-rx-route:
115 Defines the mapping of I2S RX sdis to I2S data bus lines.
117 rockchip,i2s-rx-route = <3> would mean sdi3 is receiving from data0.
[all …]
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| D | davinci-mcasp-audio.yaml | 52 0 - Inactive, 1 - TX, 2 - RX
71 - const: rx
86 rx-num-evt:
112 - description: RX interrupt
113 const: rx
114 - description: TX and RX interrupts
117 - const: rx
190 interrupt-names = "tx", "rx";
194 dma-names = "tx", "rx";
196 0 0 0 0 /* 0: INACTIVE, 1: TX, 2: RX */
[all …]
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| D | davinci-mcbsp.yaml | 40 - const: rx
44 - description: RX interrupt
49 - const: rx
77 ti,T1-framing-rx:
80 If the property is present, rx data delay is set to 2 bit clock periods.
107 interrupt-names = "rx", "tx";
110 dma-names = "tx", "rx";
|
| /Documentation/networking/device_drivers/can/freescale/ |
| D | flexcan.rst | 13 For most flexcan IP cores the driver supports 2 RX modes:
20 configured for RX-FIFO mode.
22 The RX FIFO mode uses a hardware FIFO with a depth of 6 CAN frames,
30 With the "rx-rtr" private flag the ability to receive RTR frames can
34 "rx-rtr" on
40 more performant "RX mailbox" mode and will use "RX FIFO" mode
43 "rx-rtr" off
47 This mode activates the "RX mailbox mode" for better performance, on
53 ethtool --set-priv-flags can0 rx-rtr {off|on}
|
| /Documentation/networking/device_drivers/ethernet/freescale/ |
| D | dpaa.rst | 44 -Ports / Tx Rx \ ... / Tx Rx \
62 |Rx | |Rx | |Tx | |Tx | | driver |
83 Rx Dfl FQ default reception FQ
84 Rx Err FQ Rx error frames FQ
138 On Rx, buffers for the incoming frames are retrieved from the buffers found
155 The driver has Rx and Tx checksum offloading for UDP and TCP. Currently the Rx
157 ethtool. Also, rx-flow-hash and rx-hashing was added. The addition of RSS
184 Traffic coming on the DPAA Rx queues or on the DPAA Tx confirmation
194 received on the default Rx frame queue. The default DPAA Rx frame
204 128 Rx frame queues that are configured to dedicated channels, in a
[all …]
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| /Documentation/devicetree/bindings/net/ |
| D | lantiq,etop-xway.yaml | 25 - description: RX interrupt
30 - const: rx
38 lantiq,rx-burst-length:
41 RX programmable burst length.
52 - lantiq,rx-burst-length
64 interrupt-names = "tx", "rx";
66 lantiq,rx-burst-length = <8>;
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| D | nvidia,tegra234-mgbe.yaml | 46 - const: rx-input-m
47 - const: rx-input
50 - const: rx-pcs-input
51 - const: rx-pcs-m
52 - const: rx-pcs
136 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
137 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
138 "rx-pcs", "tx-pcs";
|
| D | keystone-netcp.txt | 135 - rx-channel: the navigator packet dma channel name for rx.
136 - rx-queue: the navigator queue number associated with rx dma channel.
137 - rx-pool: specifies the number of descriptors to be used & the region-id
138 for creating the rx descriptor pool.
141 - rx-queue-depth: number of descriptors in each of the free descriptor
142 queue (FDQ) for the pktdma Rx flow. There can be at
143 present a maximum of 4 queues per Rx flow.
144 - rx-buffer-size: the buffer size for each of the Rx flow FDQ.
231 rx-channel = <22>;
232 rx-pool = <1024 12>;
[all …]
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| D | micrel-ksz90x1.txt | 49 - rxdv-skew-ps : Skew control of RX CTL pad
52 - rxd0-skew-ps : Skew control of RX data 0 pad
53 - rxd1-skew-ps : Skew control of RX data 1 pad
54 - rxd2-skew-ps : Skew control of RX data 2 pad
55 - rxd3-skew-ps : Skew control of RX data 3 pad
137 - rxc-skew-ps : Skew control of RX clock pad
142 - rxdv-skew-ps : Skew control of RX CTL pad
144 - rxd0-skew-ps : Skew control of RX data 0 pad
145 - rxd1-skew-ps : Skew control of RX data 1 pad
146 - rxd2-skew-ps : Skew control of RX data 2 pad
[all …]
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| D | intel,ixp4xx-ethernet.yaml | 30 queue-rx:
34 - description: phandle to the RX queue node
35 - description: RX queue instance to use
36 description: phandle to the RX queue on the NPE
67 - queue-rx
83 queue-rx = <&qmgr 4>;
93 queue-rx = <&qmgr 3>;
|
| /Documentation/gpu/amdgpu/ |
| D | dgpu-asic-info-table.csv | 12 Radeon RX 470 /480 /570 /580 /590 Series - AMD Radeon (TM) (Pro WX) 5100 /E9390 /E9560 /E9565 /V735…
13 Radeon (TM) (RX|Pro WX) E9260 /460 /V5300X /550 /560(X) Series, POLARIS11, DCE 11.2, 8, VCE 3.4 / U…
14 Radeon (RX/Pro) 500 /540(X) /550 /640 /WX2100 /WX3100 /WX200 Series, POLARIS12, DCE 11.2, 8, VCE 3.…
15 Radeon (RX|TM) (PRO|WX) Vega /MI25 /V320 /V340L /8200 /9100 /SSG MxGPU, VEGA10, DCE 12, 9.0.1, VCE …
20 AMD Radeon (RX|Pro) 5600(M|XT) /5700 (M|XT|XTB) /W5700, NAVI10, DCN 2.0.0, 10.1.10, VCN 2.0.0, 5.0.0
22 AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0, 10.3.0, VCN 3.0.0, 5.2.0
23 AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0, 10.3.2, VCN 3.0.0, 5.2.2
24 AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH, DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4
25 AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5
26 AMD Radeon RX 7900 XT /XTX, , DCN 3.2.0, 11.0.0, VCN 4.0.0, 6.0.0
[all …]
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| /Documentation/networking/device_drivers/ethernet/amazon/ |
| D | ena.rst | 25 processing by providing multiple Tx/Rx queue pairs (the maximum number
27 interrupt vector per Tx/Rx queue pair, adaptive interrupt moderation,
50 ena_eth_com.[ch] Tx/Rx data path.
124 I/O operations are based on Tx and Rx Submission Queues (Tx SQ and Rx
149 The Rx SQs support only the regular mode.
151 The driver supports multi-queue for both Tx and Rx. This has various
167 and Rx directions). The driver assigns an additional dedicated MSI-X vector
182 <interface name>-Tx-Rx-<queue index>
198 parameters are supported by the driver: ``tx-usecs``, ``rx-usecs``
210 .. _`RX copybreak`:
[all …]
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| /Documentation/devicetree/bindings/net/can/ |
| D | xilinx,can.yaml | 41 rx-fifo-depth:
43 description: CAN Rx fifo depth (Zynq, Axi CAN, CAN FD in sequential Rx mode)
54 description: CAN TX_OL, TX_TL and RX FIFOs have ECC support(AXI CAN)
82 - rx-fifo-depth
99 - rx-fifo-depth
117 - rx-fifo-depth
131 rx-fifo-depth = <0x40>;
143 rx-fifo-depth = <0x40>;
156 rx-fifo-depth = <0x20>;
168 rx-fifo-depth = <0x40>;
|
| /Documentation/netlink/specs/ |
| D | netdev.yaml | 36 name: rx-sg
47 name: xdp-rx-metadata
76 entries: [ rx, tx ]
107 name: xdp-rx-metadata-features
109 See Documentation/networking/xdp-rx-metadata.rst for more details.
111 enum: xdp-rx-metadata
268 doc: Queue type as rx, tx. Each queue type defines a separate ID space.
303 doc: Queue type as rx, tx, for queue-id.
317 name: rx-packets
325 name: rx-bytes
[all …]
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| D | ethtool.yaml | 179 name: rx-max
182 name: rx-mini-max
185 name: rx-jumbo-max
191 name: rx
194 name: rx-mini
197 name: rx-jumbo
203 name: rx-buf-len
215 name: rx-push
240 name: rx-frag-count
268 name: rx-min-frag-size
[all …]
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| /Documentation/networking/device_drivers/ethernet/intel/ |
| D | idpf.rst | 95 # ethtool -C <ethX> adaptive-rx off adaptive-tx off
98 - Disable adaptive ITR and lower Rx and Tx interrupts. The examples below
101 - Setting rx-usecs and tx-usecs to 80 will limit interrupts to about
104 # ethtool -C <ethX> adaptive-rx off adaptive-tx off rx-usecs 80
108 - Disable adaptive ITR and ITR by setting rx-usecs and tx-usecs to 0
111 # ethtool -C <ethX> adaptive-rx off adaptive-tx off rx-usecs 0
118 - To disable Rx adaptive ITR and set static Rx ITR to 10 microseconds or
121 # ethtool --per-queue <ethX> queue_mask 0xa --coalesce adaptive-rx off
122 rx-usecs 10
139 - Configure as many Rx/Tx queues in the VM as available. (See the idpf driver
[all …]
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| /Documentation/devicetree/bindings/serial/ |
| D | st,stm32-uart.yaml | 38 rx-tx-swap: true
46 enum: [ rx, tx ]
64 rx-threshold:
66 If value is set to 1, RX FIFO threshold is disabled.
96 rx-tx-swap: false
106 rx-threshold: false
127 dma-names = "rx", "tx";
128 rx-threshold = <4>;
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| D | rs485.yaml | 39 rs485-rx-active-high:
49 rs485-rx-during-tx:
57 rs485-rx-during-tx-gpios:
58 description: Output GPIO pin that sets the state of rs485-rx-during-tx. This
59 signal can be used to control the RX part of an RS485 transceiver. Thereby
60 the active state enables RX during TX.
|
| /Documentation/networking/device_drivers/ethernet/toshiba/ |
| D | spider_net.rst | 18 The Structure of the RX Ring.
20 The receive (RX) ring is a circular linked list of RX descriptors,
36 spidernet device driver) allocates a set of RX descriptors and RX
47 flowing RX traffic, every descr behind it should be marked "full",
55 and advance the tail pointer. Thus, when there is flowing RX traffic,
57 all of those behind it should be "not-in-use". When RX traffic is not
68 is flowing RX traffic, everything in front of the head pointer should
70 RX traffic is flowing, then the head pointer can catch up to the tail
113 The RX RAM full bug/feature
116 As long as the OS can empty out the RX buffers at a rate faster than
[all …]
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| /Documentation/devicetree/bindings/phy/ |
| D | cdns,dphy-rx.yaml | 4 $id: http://devicetree.org/schemas/phy/cdns,dphy-rx.yaml#
7 title: Cadence DPHY Rx
15 - const: cdns,dphy-rx
38 compatible = "cdns,dphy-rx";
|
| /Documentation/networking/device_drivers/ethernet/mellanox/mlx5/ |
| D | counters.rst | 134 `rx[i]_packets` will be printed as `rx0_packets` for ring 0 and `rx_packets` for
144 * - `rx[i]_packets`
148 * - `rx[i]_bytes`
190 * - `rx[i]_gro_packets`
196 * - `rx[i]_gro_bytes`
202 * - `rx[i]_gro_skbs`
207 * - `rx[i]_gro_large_hds`
212 * - `rx[i]_hds_nodata_packets`
216 * - `rx[i]_hds_nodata_bytes`
221 * - `rx[i]_hds_nosplit_packets`
[all …]
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