Searched full:rx0 (Results 1 – 19 of 19) sorted by relevance
| /Documentation/devicetree/bindings/phy/ |
| D | rockchip-mipi-dphy-rx0.yaml | 4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
24 - description: MIPI D-PHY RX0 cfg clock
53 * MIPI D-PHY RX0 use registers in "general register files", it
65 mipi_dphy_rx0: mipi-dphy-rx0 {
66 compatible = "rockchip,rk3399-mipi-dphy-rx0";
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| D | rockchip-inno-csi-dphy.yaml | 7 title: Rockchip SoC MIPI RX0 D-PHY
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| D | samsung,ufs-phy.yaml | 72 - description: symbol clock for input symbol (rx0-ch0 symbol clock)
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| /Documentation/devicetree/bindings/firmware/ |
| D | fsl,scu.yaml | 62 - description: RX0 MU channel
65 - description: RX0 MU channel
72 - description: RX0 MU channel
81 - description: RX0 MU channel
91 - const: rx0
94 - const: rx0
101 - const: rx0
110 - const: rx0
159 "rx0", "rx1", "rx2", "rx3",
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| /Documentation/devicetree/bindings/media/ |
| D | ti,j721e-csi2rx-shim.yaml | 27 - const: rx0
66 dma-names = "rx0";
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| D | rockchip-isp1.yaml | 83 description: connection point for sensors at MIPI-DPHY RX0
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| /Documentation/devicetree/bindings/net/can/ |
| D | st,stm32-bxcan.yaml | 55 - const: rx0
91 interrupt-names = "tx", "rx0", "rx1", "sce";
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| D | cc770.txt | 31 - bosch,disconnect-rx0-input : see data sheet.
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| /Documentation/devicetree/bindings/soc/rockchip/ |
| D | grf.yaml | 188 mipi-dphy-rx0:
191 $ref: /schemas/phy/rockchip-mipi-dphy-rx0.yaml#
310 mipi_dphy_rx0: mipi-dphy-rx0 {
311 compatible = "rockchip,rk3399-mipi-dphy-rx0";
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| /Documentation/devicetree/bindings/clock/ |
| D | qcom,gcc-sc8280xp.yaml | 38 - description: Primary USB4 RX0 clock
46 - description: Secondary USB4 RX0 clock
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| /Documentation/devicetree/bindings/sound/ |
| D | nvidia,tegra30-ahub.txt | 50 - rx0 .. rx<n>
84 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", "rx3", "tx3";
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| D | fsl,ssi.yaml | 80 - description: DMA controller phandle and request line for RX0
91 - const: rx0
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| D | fsl,spdif.yaml | 52 - description: Clock for tx0 and rx0.
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| D | renesas,rz-ssi.yaml | 66 MID/RID value of SSI rx0 = 0x256
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| /Documentation/devicetree/bindings/net/ |
| D | ti,icssg-prueth.yaml | 43 - const: rx0
203 "rx0", "rx1";
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| /Documentation/devicetree/bindings/spi/ |
| D | omap-spi.yaml | 116 dma-names = "tx0", "rx0";
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | qcom,ipq9574-tlmm.yaml | 80 rx0, rx1, sdc_clk, sdc_cmd, sdc_data, sdc_rclk, tsens_max,
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| D | qcom,ipq5332-tlmm.yaml | 85 qdss_tracedata_b, qspi_data, qspi_clk, qspi_cs, resout, rx0,
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| D | qcom,ipq8074-pinctrl.yaml | 86 qdss_tracedata_b, qpic, rx0, rx1, rx2, sd_card, sd_write,
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