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/Documentation/devicetree/bindings/soc/qcom/
Dqcom,geni-se.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
23 - qcom,geni-se-qup
24 - qcom,geni-se-i2c-master-hub
30 clock-names:
38 "#address-cells":
41 "#size-cells":
[all …]
/Documentation/devicetree/bindings/crypto/
Dfsl-imx-sahara.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/fsl-imx-sahara.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steffen Trumtrar <s.trumtrar@pengutronix.de>
15 - fsl,imx27-sahara
16 - fsl,imx53-sahara
23 - description: SAHARA Interrupt for Host 0
24 - description: SAHARA Interrupt for Host 1
29 - description: Sahara IPG clock
[all …]
/Documentation/devicetree/bindings/iommu/
Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
[all …]
/Documentation/devicetree/bindings/ata/
Dimx-sata.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawn.guo@linaro.org>
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
21 - fsl,imx6qp-ahci
22 - fsl,imx8qm-ahci
33 - description: sata clock
[all …]
/Documentation/devicetree/bindings/display/imx/
Dfsl,imx-lcdc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sascha Hauer <s.hauer@pengutronix.de>
11 - Pengutronix Kernel Team <kernel@pengutronix.de>
16 - enum:
17 - fsl,imx1-fb
18 - fsl,imx21-fb
19 - items:
[all …]
/Documentation/ABI/testing/
Ddebugfs-driver-dcc6 hardware if it's ready to receive user configurations.
27 What: /sys/kernel/debug/dcc/.../[list-number]/config
35 write, read-write, and loop type. The lists need to
45 echo R <addr> <n> <bus> >/sys/kernel/debug/dcc/../[list-number]/config
58 The bus type, which can be either 'apb' or 'ahb'.
59 The default is 'ahb' if leaved out.
65 echo W <addr> <n> <bus type> > /sys/kernel/debug/dcc/../[list-number]/config
76 The bus type, which can be either 'apb' or 'ahb'.
78 iii) Read-write instruction
82 echo RW <addr> <n> <mask> > /sys/kernel/debug/dcc/../[list-number]/config
[all …]
/Documentation/devicetree/bindings/misc/
Daspeed-p2a-ctrl.txt2 Device tree bindings for Aspeed AST2400/AST2500 PCI-to-AHB Bridge Control Driver
6 In this case, the host has access to a 64KiB window into all of the BMC's
14 - compatible: must be one of:
15 - "aspeed,ast2400-p2a-ctrl"
16 - "aspeed,ast2500-p2a-ctrl"
21 - reg: A hint for the memory regions associated with the P2A controller
22 - memory-region: A phandle to a reserved_memory region to be used for the PCI
23 to AHB mapping
25 The p2a-control node should be the child of a syscon node with the required
28 - compatible : Should be one of the following:
[all …]
/Documentation/devicetree/bindings/bus/
Dfsl,imx8qxp-pixel-link-msi-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
19 that is, MSI clock and AHB clock, need to be enabled so that peripherals
30 So, the controller's registers cannot be accessed by SCFW user. Hence,
32 user's point of view.
35 - $ref: simple-pm-bus.yaml#
[all …]
/Documentation/devicetree/bindings/usb/
Diproc-udc.txt3 The device node is used for UDCs integrated into Broadcom's
5 on Synopsys Designware Cores AHB Subsystem Device Controller
9 - compatible: Add the compatibility strings for supported platforms.
10 For Broadcom NS2 platform, add "brcm,ns2-udc","brcm,iproc-udc".
11 For Broadcom Cygnus platform, add "brcm,cygnus-udc", "brcm,iproc-udc".
12 - reg: Offset and length of UDC register set
13 - interrupts: description of interrupt line
14 - phys: phandle to phy node.
18 compatible = "brcm,ns2-udc", "brcm,iproc-udc";
Dchipidea,usb2-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
25 clock-names:
31 power-domains:
37 reset-names:
40 "#reset-cells":
45 itc-setting:
[all …]
Dchipidea,usb2-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
15 - enum:
16 - fsl,imx27-usb
17 - items:
18 - enum:
19 - fsl,imx23-usb
[all …]
/Documentation/devicetree/bindings/thermal/
Dmediatek,thermal.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek thermal controller for on-SoC temperatures
10 - Sascha Hauer <s.hauer@pengutronix.de>
14 via AHB bus accesses. For this reason it needs phandles to the AUXADC. Also it
15 controls a mux in the apmixedsys register space via AHB bus accesses, so a
19 - $ref: thermal-sensor.yaml#
24 - mediatek,mt2701-thermal
25 - mediatek,mt2712-thermal
[all …]
/Documentation/devicetree/bindings/net/
Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
[all …]
Dfsl,fec.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Wei Fang <wei.fang@nxp.com>
12 - NXP Linux Team <linux-imx@nxp.com>
15 - $ref: ethernet-controller.yaml#
20 - enum:
21 - fsl,imx25-fec
22 - fsl,imx27-fec
[all …]
/Documentation/devicetree/bindings/rtc/
Dmicrochip,mfps-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: rtc.yaml#
14 - Daire McNamara <daire.mcnamara@microchip.com>
15 - Lewis Hanly <lewis.hanly@microchip.com>
20 - microchip,mpfs-rtc
27 - description: |
29 - description: |
[all …]
/Documentation/devicetree/bindings/clock/
Dimx35-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx35-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steffen Trumtrar <s.trumtrar@pengutronix.de>
18 ---------------------------
27 ahb 8
105 const: fsl,imx35-ccm
113 '#clock-cells':
117 - compatible
[all …]
Dsamsung,s5pv210-audss-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-audss-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
17 include/dt-bindings/clock/s5pv210-audss.h header.
21 const: samsung,s5pv210-audss-clock
[all …]
Dimx25-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx25-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sascha Hauer <s.hauer@pengutronix.de>
18 --------------------------
26 ahb 7
152 const: fsl,imx25-ccm
160 '#clock-cells':
164 - compatible
[all …]
Dqcom,dispcc-sm6125.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Martin Botka <martin.botka@somainline.org>
16 See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h
21 - qcom,sm6125-dispcc
25 - description: Board XO source
26 - description: Byte clock from DSI PHY0
27 - description: Pixel clock from DSI PHY0
[all …]
Dqcom,sm8450-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
16 See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h
21 - qcom,sm8450-dispcc
26 - description: Board XO source
27 - description: Board Always On XO source
28 - description: Display's AHB clock
[all …]
Dqcom,sm8550-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Neil Armstrong <neil.armstrong@linaro.org>
18 - include/dt-bindings/clock/qcom,sm8550-dispcc.h
19 - include/dt-bindings/clock/qcom,sm8650-dispcc.h
20 - include/dt-bindings/clock/qcom,x1e80100-dispcc.h
25 - qcom,sm8550-dispcc
[all …]
/Documentation/devicetree/bindings/dma/
Dsnps,dma-spear1340.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
21 - enum:
[all …]
/Documentation/devicetree/bindings/sound/
Dfsl,esai.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
11 - Frank Li <Frank.Li@nxp.com>
14 The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
16 standard codecs, Sony/Phillips Digital Interface (S/PDIF) transceivers, and
22 - fsl,imx35-esai
23 - fsl,imx6ull-esai
24 - fsl,imx8qm-esai
[all …]
/Documentation/arch/arm/stm32/
Dstm32-dma-mdma-chaining.rst1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
9 ------------
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
12 further, let's introduce the peripherals involved.
38 interfaces for AHB peripherals, while the STM32 MDMA acts as a second level
39 DMA with better performance. As a AXI/AHB master, STM32 MDMA can take control
40 of the AXI/AHB bus.
44 ----------
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
[all …]
/Documentation/devicetree/bindings/display/
Darm,pl11x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liviu Dudau <Liviu.Dudau@arm.com>
11 - Andre Przywara <andre.przywara@arm.com>
24 - arm,pl110
25 - arm,pl111
27 - compatible
32 - enum:
33 - arm,pl110
[all …]

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