Home
last modified time | relevance | path

Searched +full:sata +full:- +full:phy (Results 1 – 25 of 55) sorted by relevance

123

/Documentation/devicetree/bindings/phy/
Dbrcm,sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SATA3 PHY
10 - Florian Fainelli <f.fainelli@gmail.com>
14 pattern: "^sata[-|_]phy(@.*)?$"
18 - items:
19 - enum:
20 - brcm,bcm7216-sata-phy
[all …]
Dqcom,sata-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SATA PHY Controller
10 - Bjorn Andersson <andersson@kernel.org>
11 - Konrad Dybcio <konrad.dybcio@linaro.org>
14 The Qualcomm SATA PHY describes on-chip SATA Physical layer controllers.
19 - qcom,ipq806x-sata-phy
20 - qcom,apq8064-sata-phy
[all …]
Dphy-mvebu.txt1 * Marvell MVEBU SATA PHY
3 Power control for the SATA phy found on Marvell MVEBU SoCs.
5 This document extends the binding described in phy-bindings.txt
9 - reg : Offset and length of the register set for the SATA device
10 - compatible : Should be "marvell,mvebu-sata-phy"
11 - clocks : phandle of clock and specifier that supplies the device
12 - clock-names : Should be "sata"
15 sata-phy@84000 {
16 compatible = "marvell,mvebu-sata-phy";
19 clock-names = "sata";
[all …]
Dberlin-sata-phy.txt1 Berlin SATA PHY
2 ---------------
5 - compatible: should be one of
6 "marvell,berlin2-sata-phy"
7 "marvell,berlin2q-sata-phy"
8 - address-cells: should be 1
9 - size-cells: should be 0
10 - phy-cells: from the generic PHY bindings, must be 1
11 - reg: address and length of the register
12 - clocks: reference to the clock entry
[all …]
Dphy-miphy365x.txt1 STMicroelectronics STi MIPHY365x PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
5 for SATA and PCIe.
8 - compatible : Should be "st,miphy365x-phy"
9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
11 an entry for each port sub-node, specifying the control
14 Required nodes : A sub-node is required for each channel the controller
16 'reg' and 'reg-names' properties are used inside these
21 - #phy-cells : Should be 1 (See second example)
23 - PHY_TYPE_SATA
[all …]
Dhix5hd2-phy.txt1 Hisilicon hix5hd2 SATA PHY
2 -----------------------
5 - compatible: should be "hisilicon,hix5hd2-sata-phy"
6 - reg: offset and length of the PHY registers
7 - #phy-cells: must be 0
8 Refer to phy/phy-bindings.txt for the generic PHY binding properties
11 - hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
12 - hisilicon,power-reg: offset and bit number within peripheral-syscon,
13 register of controlling sata power supply.
16 sata_phy: phy@f9900000 {
[all …]
Dsamsung,exynos5250-sata-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,exynos5250-sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5250 SoC SATA PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
16 const: samsung,exynos5250-sata-phy
21 clock-names:
[all …]
Dphy-miphy28lp.txt1 STMicroelectronics STi MIPHY28LP PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
5 for SATA, PCIe or USB3.
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
10 which contain the SATA, PCIe or USB3 mode setting bits.
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
19 - #phy-cells : Should be 1 (See second example)
21 - PHY_TYPE_SATA
[all …]
Dcalxeda-combophy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/calxeda-combophy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda Highbank Combination PHYs for SATA
11 and to SATA connectors. The PHYs support multiple protocols (SATA,
12 SGMII, PCIe) and can be assigned to different devices (SATA or XGMAC
15 not by a dedicated PHY driver.
18 - Andre Przywara <andre.przywara@arm.com>
22 const: calxeda,hb-combophy
[all …]
Dfsl,imx8qm-hsio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8QM SoC series High Speed IO(HSIO) SERDES PHY
10 - Richard Zhu <hongxing.zhu@nxp.com>
15 - fsl,imx8qm-hsio
16 - fsl,imx8qxp-hsio
19 - description: Base address and length of the PHY block
20 - description: HSIO control and status registers(CSR) of the PHY
[all …]
Dst-spear-miphy.txt4 ST Microelectronics SPEAr miphy is a phy controller supporting PCIe and SATA.
7 - compatible : should be "st,spear1310-miphy" or "st,spear1340-miphy"
8 - reg : offset and length of the PHY register set.
9 - misc: phandle for the syscon node to access misc registers
10 - #phy-cells : from the generic PHY bindings, must be 1.
11 - cell[1]: 0 if phy used for SATA, 1 for PCIe.
14 - phy-id: Instance id of the phy. Only required when there are multiple phys
Dhisilicon,hi3798cv200-combphy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/hisilicon,hi3798cv200-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon STB PCIE/SATA/USB3 PHY
10 - Shawn Guo <shawn.guo@linaro.org>
14 const: hisilicon,hi3798cv200-combphy
19 '#phy-cells':
20 description: The cell contains the PHY mode
29 hisilicon,fixed-mode:
[all …]
Dti-phy.txt1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
3 OMAP CONTROL PHY
6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
11 e.g. USB3 PHY and SATA PHY on OMAP5.
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
14 e.g. PCIE PHY in DRA7x
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
[all …]
/Documentation/devicetree/bindings/ata/
Dapm-xgene.txt1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
4 controllers. Each SATA controller (pair of ports) have its own node.
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
19 - interrupts : Interrupt-specifier for SATA host controller IRQ.
20 - clocks : Reference to the clock entry.
21 - phys : A list of phandles + phy-specifiers, one for each
22 entry in phy-names.
[all …]
Dahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
14 This document defines device tree properties for a common AHCI SATA
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
24 - $ref: sata-common.yaml#
[all …]
Dimx-sata.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX AHCI SATA Controller
10 - Shawn Guo <shawn.guo@linaro.org>
13 The Freescale i.MX SATA controller mostly conforms to the AHCI interface
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
21 - fsl,imx6qp-ahci
[all …]
Dmarvell.txt1 * Marvell Orion SATA
4 - compatibility : "marvell,orion-sata" or "marvell,armada-370-sata"
5 - reg : Address range of controller
6 - interrupts : Interrupt controller is using
7 - nr-ports : Number of SATA ports in use.
10 - phys : List of phandles to sata phys
11 - phy-names : Should be "0", "1", etc, one number per phandle
15 sata@80000 {
16 compatible = "marvell,orion-sata";
20 phy-names = "0", "1";
[all …]
Drockchip,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller for Rockchip devices
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller found in Rockchip
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
25 - compatible
[all …]
Dahci-st.txt1 STMicroelectronics STi SATA controller
3 This binding describes a SATA device.
6 - compatible : Must be "st,ahci"
7 - reg : Physical base addresses and length of register sets
8 - interrupts : Interrupt associated with the SATA device
9 - interrupt-names : Associated name must be; "hostc"
10 - clocks : The phandle for the clock
11 - clock-names : Associated name must be; "ahci_clk"
12 - phys : The phandle for the PHY port
13 - phy-names : Associated name must be; "ahci_phy"
[all …]
Dnvidia,tegra-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra AHCI SATA Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra124-ahci
17 - nvidia,tegra132-ahci
18 - nvidia,tegra210-ahci
[all …]
Dsnps,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller.
20 - snps,dwc-ahci
21 - snps,spear-ahci
23 - compatible
[all …]
Dallwinner,sun8i-r40-ahci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/allwinner,sun8i-r40-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner R40 AHCI SATA Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
15 const: allwinner,sun8i-r40-ahci
22 - description: AHCI Bus Clock
23 - description: AHCI Module Clock
[all …]
Dmediatek,mtk-ahci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ata/mediatek,mtk-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ryder Lee <ryder.lee@mediatek.com>
13 - $ref: ahci-common.yaml#
18 - enum:
19 - mediatek,mt7622-ahci
20 - const: mediatek,mtk-ahci
28 interrupt-names:
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra124-xusb-padctl.txt6 required for PCIe and SATA, it lacks the flexibility to represent the features
7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
12 associated PHY that must be powered up before the pad can be used.
14 This document defines the device-specific binding for the XUSB pad controller.
16 Refer to pinctrl-bindings.txt in this directory for generic information about
17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on
21 --------------------
22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
23 Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
24 "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
[all …]
/Documentation/devicetree/bindings/scsi/
Dhisilicon-sas.txt3 The HiSilicon SAS controller supports SAS/SATA.
6 - compatible : value should be as follows:
7 (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
8 (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
9 (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset
10 - sas-addr : array of 8 bytes for host SAS address
11 - reg : Contains two regions. The first is the address and length of the SAS
15 - hisilicon,sas-syscon: phandle of syscon used for sas control
16 - ctrl-reset-reg : offset to controller reset register in ctrl reg
17 - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg
[all …]

123