Searched full:sclk (Results 1 – 25 of 33) sorted by relevance
12
| /Documentation/devicetree/bindings/rtc/ |
| D | moxa,moxart-rtc.txt | 6 - rtc-sclk-gpios : RTC sclk gpio, with zero flags
14 rtc-sclk-gpios = <&gpio 5 0>;
|
| /Documentation/devicetree/bindings/clock/ |
| D | nvidia,tegra20-car.yaml | 46 "^(sclk)|(pll-[cem])$":
51 - nvidia,tegra20-sclk
52 - nvidia,tegra30-sclk
93 sclk {
94 compatible = "nvidia,tegra20-sclk";
|
| D | allwinner,sun4i-a10-tcon-ch0-clk.yaml | 65 clock-output-names = "tcon-ch0-sclk";
74 clock-output-names = "tcon-ch1-sclk";
|
| /Documentation/devicetree/bindings/crypto/ |
| D | rockchip,rk3288-crypto.yaml | 55 - const: sclk
75 - const: sclk
94 - const: sclk
124 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
|
| /Documentation/devicetree/bindings/media/ |
| D | samsung,s5pv210-jpeg.yaml | 85 - const: sclk
103 - const: sclk
116 clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
|
| D | rockchip-rga.yaml | 43 - const: sclk
80 clock-names = "aclk", "hclk", "sclk";
|
| /Documentation/devicetree/bindings/timer/ |
| D | renesas,em-sti.yaml | 26 const: sclk
45 clock-names = "sclk";
|
| /Documentation/devicetree/bindings/i2c/ |
| D | renesas,iic-emev2.yaml | 29 const: sclk
51 clock-names = "sclk";
|
| /Documentation/devicetree/bindings/sound/ |
| D | amlogic,axg-tdm-iface.yaml | 32 - const: sclk
54 clock-names = "sclk", "lrclk", "mclk";
|
| D | cirrus,ep9301-i2s.yaml | 40 - const: sclk
77 clock-names = "mclk", "sclk", "lrclk";
|
| D | amlogic,axg-tdm-formatters.yaml | 33 - const: sclk
86 clock-names = "pclk", "sclk", "sclk_sel",
|
| D | cs35l34.txt | 45 SCLK. Otherwise, data is on the falling edge of SCLK.
|
| D | ti,pcm512x.yaml | 37 description: A clock specifier for the clock connected as SCLK. If this is
55 external connection from the pll-out pin to the SCLK pin is assumed.
|
| D | fsl,sgtl5000.yaml | 69 sclk-strength:
71 The SCLK pad strength. Possible values are: 0, 1, 2 and 3 as per the
|
| /Documentation/devicetree/bindings/serial/ |
| D | renesas,em-uart.yaml | 38 - const: sclk
73 clock-names = "sclk";
|
| /Documentation/devicetree/bindings/iio/resolver/ |
| D | adi,ad2s90.yaml | 27 application of SCLK, as also specified. And since the delay is not
28 implemented in the spi code, to satisfy it, SCLK's period should be at
|
| /Documentation/devicetree/bindings/iio/adc/ |
| D | samsung,exynos-adc.yaml | 43 Must contain clock names (adc, sclk) matching phandles in clocks
110 - const: sclk
164 clock-names = "adc", "sclk";
|
| /Documentation/devicetree/bindings/spi/ |
| D | spi_oc_tiny.txt | 9 the input clock to SCLK.
|
| /Documentation/iio/ |
| D | ad4000.rst | 62 +--------------------| SCLK |
87 +--------------------| SCLK |
104 +--------------------| SCLK |
130 +--------------------| SCLK |
|
| D | ad4695.rst | 44 | SCLK |<--------| SCLK |
|
| /Documentation/devicetree/bindings/i3c/ |
| D | silvaco,i3c-master.yaml | 53 clocks = <&zynqmp_clk 71>, <&fclk>, <&sclk>;
|
| /Documentation/devicetree/bindings/mmc/ |
| D | cavium-mmc.txt | 37 clocks = <&sclk>;
|
| /Documentation/devicetree/bindings/watchdog/ |
| D | marvell,cn10624-wdt.yaml | 77 clocks = <&sclk>;
|
| /Documentation/hwmon/ |
| D | lm70.rst | 45 the driver accesses the LM70 using SPI communication: 16 SCLK cycles
|
| /Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,dove-pinctrl.txt | 30 mpp10 10 gpio, pmu, ssp(sclk), pmu*
51 lcd-spi(sck), ssp(sclk)
|
12