Searched full:sdma (Results 1 – 22 of 22) sorted by relevance
| /Documentation/devicetree/bindings/dma/ |
| D | fsl,imx-sdma.yaml | 4 $id: http://devicetree.org/schemas/dma/fsl,imx-sdma.yaml#
7 title: Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
20 - fsl,imx50-sdma
21 - fsl,imx51-sdma
22 - fsl,imx53-sdma
23 - fsl,imx6q-sdma
24 - fsl,imx7d-sdma
25 - const: fsl,imx35-sdma
28 - fsl,imx6sx-sdma
29 - fsl,imx6sl-sdma
[all …]
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| D | ti-dma-crossbar.txt | 34 sdma: dma-controller@4a056000 {
35 compatible = "ti,omap4430-sdma";
53 /* Protect the sDMA request ranges: 10-14 and 100-126 */
55 dma-masters = <&sdma>;
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| /Documentation/devicetree/bindings/bus/ |
| D | fsl,spba-bus.yaml | 17 "simple-bus" because the SDMA controller uses this compatible flag to
19 the SDMA can access. There are no special clocks for the bus, because
20 the SDMA controller itself has its interrupt and clock assignments.
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| /Documentation/devicetree/bindings/sound/ |
| D | fsl,imx-asrc.yaml | 170 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
171 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
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| D | ti,omap4-mcpdm.yaml | 69 dmas = <&sdma 65>, <&sdma 66>;
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| D | fsl,esai.yaml | 113 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
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| D | fsl,spdif.yaml | 139 dmas = <&sdma 14 18 0>,
140 <&sdma 15 18 0>;
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| D | fsl,ssi.yaml | 190 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
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| /Documentation/gpu/amdgpu/ |
| D | debugging.rst | 37 hub used for graphics, compute, and sdma on some chips. mmhub is the
38 memory hub used for multi-media and sdma on some chips.
56 - SDMA: SDMA engines
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| D | apu-asic-info-table.csv | 1 Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN version, SDMA version, MP0 v…
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| D | amdgpu-glossary.rst | 104 SDMA
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| D | driver-core.rst | 11 E.g., you might have two different ASICs that both have System DMA (SDMA) 5.x IPs.
60 SDMA (System DMA)
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| D | dgpu-asic-info-table.csv | 1 Product Name, Code Reference, DCN/DCE version, GC version, VCN version, SDMA version
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| /Documentation/devicetree/bindings/mmc/ |
| D | ti-omap.txt | 24 dmas = <&sdma 61 &sdma 62>;
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| D | sdhci-omap.txt | 41 dmas = <&sdma 61 &sdma 62>;
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| /Documentation/devicetree/bindings/crypto/ |
| D | omap-des.txt | 26 dmas = <&sdma 117>, <&sdma 116>;
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| /Documentation/devicetree/bindings/mtd/ |
| D | cadence-nand-controller.txt | 9 - reg-names: should contain "reg" and "sdma"
40 reg-names = "reg", "sdma";
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| /Documentation/devicetree/bindings/spi/ |
| D | cdns,xspi.yaml | 35 - const: sdma
85 reg-names = "io", "sdma", "aux";
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| /Documentation/devicetree/bindings/serial/ |
| D | 8250_omap.yaml | 113 dmas = <&sdma 81 &sdma 82>;
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| D | fsl-imx-uart.yaml | 149 dmas = <&sdma 18 4 1>, <&sdma 19 4 2>;
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| /Documentation/ABI/stable/ |
| D | sysfs-class-infiniband | 700 sdma<N>/ contains one directory per sdma engine (0 - 15)
703 cpu_list: (RW) List of cpus for user-process to sdma
706 vl: (RO) Displays the virtual lane (vl) the sdma
711 for the device. As an example, to set an sdma engine irq
713 sdma engine, which is "near" in terms of NUMA configuration, or
726 uses vl=0, then sdma engine 3 is selected by the driver, and
727 also the interrupt of the sdma engine 3 is steered to cpu 3.
729 vl=1, then engine 4 will be selected and the irq of the sdma
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpc5200.txt | 177 fourth group, SDMA.
182 L1 := [CRIT=0, MAIN=1, PERP=2, SDMA=3]
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