| /Documentation/devicetree/bindings/crypto/ |
| D | fsl-sec2.txt | 1 Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
6 SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3)
10 - interrupts : the SEC's interrupt number
17 should be encoded following the SEC's Descriptor Header Dword
21 bit 1 = set if SEC has the ARC4 EU (AFEU)
22 bit 2 = set if SEC has the DES/3DES EU (DEU)
23 bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
24 bit 4 = set if SEC has the random number generator EU (RNG)
25 bit 5 = set if SEC has the public key EU (PKEU)
26 bit 6 = set if SEC has the AES EU (AESU)
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| D | fsl-sec6.txt | 1 SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
2 Currently Freescale powerpc chip C29X is embedded with SEC 6.
3 SEC 6 device tree binding include:
4 -SEC 6 Node
9 SEC 6 Node
13 Node defines the base address of the SEC 6 block.
15 configuration registers for the SEC 6 block.
16 For example, In C293, we could see three SEC 6 node.
23 Definition: Must include "fsl,sec-v6.0".
25 - fsl,sec-era
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| D | fsl,sec-v4.0.yaml | 5 $id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
8 title: Freescale SEC 4
16 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
19 SEC 4 h/w can process requests from 2 types of sources.
20 1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
21 2. Job Rings (HW interface between cores & SEC 4 registers).
25 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
28 SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
41 - const: fsl,sec-v5.4
42 - const: fsl,sec-v5.0
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| D | fsl,sec-v4.0-mon.yaml | 5 $id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0-mon.yaml#
24 - const: fsl,sec-v4.0-mon
28 - const: fsl,sec-v5.0-mon
29 - const: fsl,sec-v4.0-mon
32 - fsl,sec-v5.3-mon
33 - fsl,sec-v5.4-mon
34 - const: fsl,sec-v5.0-mon
35 - const: fsl,sec-v4.0-mon
51 const: fsl,sec-v4.0-mon-rtc-lp
88 const: fsl,sec-v4.0-pwrkey
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| D | hisilicon,hip07-sec.txt | 1 * Hisilicon hip07 Security Accelerator (SEC)
5 - "hisilicon,hip06-sec"
6 - "hisilicon,hip07-sec"
16 Interrupt 0 is for the SEC unit error queue.
22 - iommus: The SEC units are behind smmu-v3 iommus.
28 compatible = "hisilicon,hip07-sec";
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| /Documentation/driver-api/firmware/ |
| D | fw_upload.rst | 43 struct m10bmc_sec *sec;
47 sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL);
48 if (!sec)
51 sec->dev = &pdev->dev;
52 sec->m10bmc = dev_get_drvdata(pdev->dev.parent);
53 dev_set_drvdata(&pdev->dev, sec);
55 fw_name = dev_name(sec->dev);
58 sec->fw_name = kmemdup_nul(fw_name, len, GFP_KERNEL);
60 fwl = firmware_upload_register(THIS_MODULE, sec->dev, sec->fw_name,
61 &m10bmc_ops, sec);
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| /Documentation/ABI/testing/ |
| D | debugfs-hisi-sec | 5 the SEC debug registers.
7 Only available for PF, and take no other effect on SEC.
12 Description: One SEC controller has one PF and multiple VFs, each function
21 SEC driver supports to configure each function's QoS, the driver
37 Description: One QM of SEC may contain multiple queues. Select specific
45 the SEC's QM debug registers.
47 Only available for PF, and take no other effect on SEC.
54 Available for both PF and VF, and take no other effect on SEC.
60 Available for both PF and VF, and take no other effect on SEC.
66 Available for both PF and VF, and take no other effect on SEC.
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| D | sysfs-driver-intel-m10-bmc-sec-update | 1 What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_root_entry_hash
11 What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_root_entry_hash
21 What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_root_entry_hash
31 What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_canceled_csks
39 What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_canceled_csks
47 What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_canceled_csks
55 What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/flash_count
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| /Documentation/translations/zh_CN/PCI/ |
| D | acpi-info.rst | 78 [1] ACPI 6.2, sec 6.1:
82 [2] ACPI 6.2, sec 3.7:
89 [3] ACPI 6.2, sec 6.2:
101 [4] ACPI 6.2, sec 6.4.3.5.1, 2, 3, 4:
111 [5] ACPI 6.2, sec 19.6.43:
115 [6] PCI Firmware 3.2, sec 4.1.2:
122 [7] PCI Express 4.0, sec 7.2.2:
126 [8] PCI Firmware 3.2, sec 4.1.2:
132 [9] PCI Firmware 3.2, sec 4.1.3:
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| /Documentation/devicetree/bindings/nvmem/ |
| D | qcom,sec-qfprom.yaml | 4 $id: http://devicetree.org/schemas/nvmem/qcom,sec-qfprom.yaml#
25 - qcom,qdu1000-sec-qfprom
26 - const: qcom,sec-qfprom
45 compatible = "qcom,qdu1000-sec-qfprom", "qcom,sec-qfprom";
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| /Documentation/devicetree/bindings/watchdog/ |
| D | atmel,at91sam9-wdt.yaml | 26 atmel,max-heartbeat-sec:
32 atmel,min-heartbeat-sec:
35 must be smaller than the max-heartbeat-sec value. It is used to
120 timeout-sec = <15>;
125 atmel,max-heartbeat-sec = <16>;
126 atmel,min-heartbeat-sec = <0>;
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| D | ts4800-wdt.txt | 11 - timeout-sec: contains the watchdog timeout in seconds.
23 timeout-sec = <10>;
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| D | marvel.txt | 35 - timeout-sec : Contains the watchdog timeout in seconds
43 timeout-sec = <10>;
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| /Documentation/usb/ |
| D | ehci.rst | 11 - "High Speed" 480 Mbit/sec (60 MByte/sec)
12 - "Full Speed" 12 Mbit/sec (1.5 MByte/sec)
13 - "Low Speed" 1.5 Mbit/sec
155 them. The 480 Mbit/sec "raw transfer rate" is obeyed by all devices,
165 So more than 50 MByte/sec is available for bulk transfers, when both
168 approach the quoted 480 MBit/sec transfer rate.
174 20 MByte/sec transfer rates. This is of course subject to change;
178 at around 28 MByte/sec aggregate transfer rate. While this is clearly
179 enough for a single device at 20 MByte/sec, putting three such devices
180 onto one bus does not get you 60 MByte/sec. The issue appears to be
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| /Documentation/hid/ |
| D | hidreport-parsing.rst | 31 --------- Function of the item (see HID spec 6.2.2.7, then HUT Sec 3)
35 we need to refer to HUT Sec 3.
39 Sec. 3, "Usage Pages"; from there, one sees that ``0x01`` stands for
45 (``0000``) is given in the HID spec Sec. 6.2.2.8 "Local Items", so that
46 we have a ``Usage``. From HUT, Sec. 4, "Generic Desktop Page", we see that
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| D | hid-bpf.rst | 157 1. event processing/filtering with ``SEC("struct_ops/hid_device_event")`` in libbpf
158 2. actions coming from userspace with ``SEC("syscall")`` in libbpf
159 3. change of the report descriptor with ``SEC("struct_ops/hid_rdesc_fixup")`` or
160 ``SEC("struct_ops.s/hid_rdesc_fixup")`` in libbpf
176 Note that ``hid_rdesc_fixup`` can be declared as sleepable (``SEC("struct_ops.s/hid_rdesc_fixup")``…
261 ``SEC("struct_ops/hid_device_event")``
277 ``SEC("syscall")``
291 ``SEC("struct_ops/hid_rdesc_fixup")``
304 Whenever a struct_ops containing a ``SEC("struct_ops/hid_rdesc_fixup")`` program
377 char _license[] SEC("license") = "GPL";
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| /Documentation/watchdog/ |
| D | mlx-wdt.rst | 17 e.g. timeout 20 sec will be rounded up to 32768 msec.
18 The maximum timeout period is 32 sec (32768 msec.),
22 Actual HW timeout is defined in sec. and it's the same as
24 Maximum timeout is 255 sec.
29 Maximum timeout is 65535 sec.
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| /Documentation/userspace-api/media/dvb/ |
| D | frontend.rst | 28 - Satellite Equipment Control (SEC) [#f1]_.
42 Control (SEC) allows to power control and to send/receive signals to
45 Horn (LNBf). It supports the DiSEqC and V-SEC protocols. The DiSEqC
46 (digital SEC) specification is available at
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| /Documentation/hwmon/ |
| D | asc7621.rst | 277 * 0 0 Sec. (no Smoothing) (default)
278 * 1 0.25 Sec.
279 * 2 0.5 Sec.
280 * 3 1.0 Sec.
281 * 4 2.0 Sec.
282 * 5 4.0 Sec.
283 * 6 8.0 Sec.
284 * 7 0.0 Sec.
302 0 0.25 Sec.
303 1 1.1 Sec.
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| D | max31827.rst | 83 - 64000 (ms) = 1 conv/64 sec
84 - 32000 (ms) = 1 conv/32 sec
85 - 16000 (ms) = 1 conv/16 sec
86 - 4000 (ms) = 1 conv/4 sec
87 - 1000 (ms) = 1 conv/sec (default)
88 - 250 (ms) = 4 conv/sec
89 - 125 (ms) = 8 conv/sec
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| /Documentation/userspace-api/media/drivers/ |
| D | max2175.rst | 53 samples/sec with a 10.24 MHz sck.
56 samples/sec with a 32.768 MHz sck.
61 samples/sec with a 14.88375 MHz sck.
64 samples/sec with a 7.441875 MHz sck.
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| /Documentation/devicetree/bindings/rtc/ |
| D | xlnx,zynqmp-rtc.yaml | 45 - const: sec
49 calibration value for 1 sec period which will
79 interrupt-names = "alarm", "sec";
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| /Documentation/PCI/ |
| D | acpi-info.rst | 100 [1] ACPI 6.2, sec 6.1:
106 [2] ACPI 6.2, sec 3.7:
117 [3] ACPI 6.2, sec 6.2:
136 [4] ACPI 6.2, sec 6.4.3.5.1, 2, 3, 4:
146 [5] ACPI 6.2, sec 19.6.43:
152 [6] PCI Firmware 3.2, sec 4.1.2:
164 [7] PCI Express 4.0, sec 7.2.2:
170 [8] PCI Firmware 3.2, sec 4.1.2:
180 [9] PCI Firmware 3.2, sec 4.1.3:
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| /Documentation/devicetree/bindings/clock/ |
| D | fujitsu,mb86s70-crg11.txt | 21 interrupts = <0 36 4>, /* LP Non-Sec */
22 <0 35 4>, /* HP Non-Sec */
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| /Documentation/devicetree/bindings/misc/ |
| D | qemu,vcpu-stall-detector.yaml | 35 timeout-sec:
55 timeout-sec = <8>;
|