Searched +full:secure +full:- +full:only (Results 1 – 25 of 150) sorted by relevance
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| /Documentation/devicetree/bindings/arm/ |
| D | secure.txt | 1 * ARM Secure world bindings
4 "Normal" and "Secure". Most devicetree consumers (including the Linux
6 world or the Secure world. However some devicetree consumers are
8 visible only in the Secure address space, only in the Normal address
10 virtual machine which boots Secure firmware and wants to tell the
13 The general principle of the naming scheme for Secure world bindings
14 is that any property that needs a different value in the Secure world
15 can be supported by prefixing the property name with "secure-". So for
16 instance "secure-foo" would override "foo". For property names with
17 a vendor prefix, the Secure variant of "vendor,foo" would be
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| D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
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| D | arm,corstone1000.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
11 - Hugues Kamba Mpiana <hugues.kambampiana@arm.com>
14 ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
19 systems for M-Class (or other) processors for adding sensors, connectivity,
21 a secure SoC for a range of rich IoT applications, for example gateways, smart
24 Integrated Secure Enclave providing hardware Root of Trust and supporting
25 seamless integration of the optional CryptoCell™-312 cryptographic
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| /Documentation/devicetree/bindings/crypto/ |
| D | inside-secure,safexcel.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/crypto/inside-secure,safexcel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Inside Secure SafeXcel cryptographic engine
10 - Antoine Tenart <atenart@kernel.org>
15 - const: inside-secure,safexcel-eip197b
16 - const: inside-secure,safexcel-eip197d
17 - const: inside-secure,safexcel-eip97ies
18 - const: inside-secure,safexcel-eip197
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| D | fsl-dcp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/fsl-dcp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale DCP (Data Co-Processor) found on i.MX23/i.MX28
10 - Marek Vasut <marex@denx.de>
15 - enum:
16 - fsl,imx23-dcp
17 - fsl,imx28-dcp
18 - items:
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| /Documentation/devicetree/bindings/nvmem/ |
| D | st,stm32-romem.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
19 - $ref: nvmem.yaml#
20 - $ref: nvmem-deprecated-cells.yaml#
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| D | amlogic,meson-gxbb-efuse.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/amlogic,meson-gxbb-efuse.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 - $ref: nvmem.yaml#
14 - $ref: nvmem-deprecated-cells.yaml#
19 - const: amlogic,meson-gxbb-efuse
20 - items:
21 - const: amlogic,meson-gx-efuse
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| D | qcom,sec-qfprom.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/qcom,sec-qfprom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies Inc, Secure QFPROM Efuse
10 - Komal Bajaj <quic_kbajaj@quicinc.com>
14 protected from non-secure access. In such situations, the OS have to use
15 secure calls to read the region.
18 - $ref: nvmem.yaml#
19 - $ref: nvmem-deprecated-cells.yaml#
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| /Documentation/arch/powerpc/ |
| D | ultravisor.rst | 1 .. SPDX-License-Identifier: GPL-2.0
15 POWER 9 that enables Secure Virtual Machines (SVMs). DD2.3 chips
16 (PVR=0x004e1203) or greater will be PEF-capable. A new ISA release
25 +------------------+
29 +------------------+
31 +------------------+
33 +------------------+
35 +------------------+
38 VMs in the system. SVMs are protected while at rest and can only be
56 process is running in secure mode, MSR(S) bit 41. MSR(S)=1, process
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| /Documentation/devicetree/bindings/mailbox/ |
| D | ti,secure-proxy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,secure-proxy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments' Secure Proxy
10 - Nishanth Menon <nm@ti.com>
13 The Texas Instruments' secure proxy is a mailbox controller that has
16 called "threads" or "proxies" - each instance is unidirectional and is
22 pattern: "^mailbox@[0-9a-f]+$"
25 const: ti,am654-secure-proxy
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| D | arm,mhu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jassi Brar <jaswinder.singh@linaro.org>
13 The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3
19 be a 'Secure' resource, hence can't be used by Linux running NS.
22 interrupt signal using a 32-bit register, with all 32-bits logically ORed
28 interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote
37 - arm,mhu
38 - arm,mhu-doorbell
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| /Documentation/devicetree/bindings/rng/ |
| D | omap_rng.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: OMAP SoC and Inside-Secure HWRNG Module
10 - Jayesh Choudhary <j-choudhary@ti.com>
15 - ti,omap2-rng
16 - ti,omap4-rng
17 - inside-secure,safexcel-eip76
33 - description: EIP150 gateable clock
34 - description: Main gateable clock
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| D | ti,omap-rom-rng.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/rng/ti,omap-rom-rng.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pali Rohár <pali@kernel.org>
11 - Tony Lindgren <tony@atomide.com>
14 Secure SoCs may provide RNG via secure ROM calls like Nokia N900 does.
15 The implementation can depend on the SoC secure ROM used.
19 const: nokia,n900-rom-rng
24 clock-names:
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| /Documentation/devicetree/bindings/firmware/ |
| D | brcm,kona-smc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/firmware/brcm,kona-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Kona family Secure Monitor bounce buffer
10 A bounce buffer used for non-secure to secure communications.
13 - Florian Fainelli <f.fainelli@gmail.com>
18 - enum:
19 - brcm,bcm11351-smc
20 - brcm,bcm21664-smc
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| D | intel,stratix10-svc.txt | 3 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
4 processor system (HPS) and Secure Device Manager (SDM). When the FPGA is
10 communication with SDM, only the secure world of software (EL3, Exception
18 driver also manages secure monitor call (SMC) to communicate with secure monitor
22 -------------------
26 - compatible: "intel,stratix10-svc" or "intel,agilex-svc"
27 - method: smc or hvc
28 smc - Secure Monitor Call
29 hvc - Hypervisor Call
30 - memory-region:
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| D | amlogic,meson-gxbb-sm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/amlogic,meson-gxbb-sm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic Secure Monitor (SM)
10 In the Amlogic SoCs the Secure Monitor code is used to provide access to the
14 - Neil Armstrong <neil.armstrong@linaro.org>
19 - const: amlogic,meson-gxbb-sm
20 - items:
21 - const: amlogic,meson-gx-sm
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| /Documentation/ABI/testing/ |
| D | sysfs-secvar | 5 secureboot, thereby secure variables. It exposes interface
6 for reading/writing the secure variables
11 Description: This directory lists all the secure variables that are supported
22 and is expected to be "ibm,edk2-compat-v1".
26 has the form "ibm,plpks-sb-v<version>", or
27 "ibm,plpks-sb-unknown" if there is no SB_VERSION variable.
32 Description: Each secure variable is represented as a directory named as
46 Description: A read-only file containing the value of the variable. The size
52 Description: A write-only file that is used to submit the new value for the
59 Description: This optional directory contains read-only config attributes as
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| /Documentation/devicetree/bindings/arm/amlogic/ |
| D | amlogic,meson-mx-secbus2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/amlogic/amlogic,meson-mx-secbus2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
14 contains registers for various IP blocks such as pin-controller bits for
16 The registers can be accessed directly when not running in "secure mode".
17 When "secure mode" is enabled then these registers have to be accessed
18 through secure monitor calls.
23 - enum:
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| /Documentation/virt/kvm/s390/ |
| D | s390-pv.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 -------
15 Each guest starts in non-protected mode and then may make a request to
20 The Ultravisor will secure and decrypt the guest's boot memory
33 -------------------
46 safeguarding; they can only be injected for instructions that have
54 -------------------------------
64 ---------------------
70 The control structures associated with SIE provide the Secure
72 Secure Interception General Register Save Area. Guest GRs and most of
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| /Documentation/tee/ |
| D | amd-tee.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 AMD-TEE (AMD's Trusted Execution Environment)
7 The AMD-TEE driver handles the communication with AMD's TEE environment. The
8 TEE environment is provided by AMD Secure Processor.
10 The AMD Secure Processor (formerly called Platform Security Processor or PSP)
12 software-based Trusted Execution Environment (TEE) designed to enable
13 third-party Trusted Applications. This feature is currently enabled only for
16 The following picture shows a high level overview of AMD-TEE::
21 User space (Kernel space) | AMD Secure Processor (PSP)
24 +--------+ | +-------------+
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| D | op-tee.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 OP-TEE (Open Portable Trusted Execution Environment)
7 The OP-TEE driver handles OP-TEE [1] based TEEs. Currently it is only the ARM
8 TrustZone based OP-TEE solution that is supported.
10 Lowest level of communication with OP-TEE builds on ARM SMC Calling
11 Convention (SMCCC) [2], which is the foundation for OP-TEE's SMC interface
12 [3] used internally by the driver. Stacked on top of that is OP-TEE Message
15 OP-TEE SMC interface provides the basic functions required by SMCCC and some
16 additional functions specific for OP-TEE. The most interesting functions are:
18 - OPTEE_SMC_FUNCID_CALLS_UID (part of SMCCC) returns the version information
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| /Documentation/devicetree/bindings/iommu/ |
| D | qcom,iommu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konradybcio@kernel.org>
13 Qualcomm "B" family devices which are not compatible with arm-smmu have
16 to non-secure vs secure interrupt line.
21 - items:
22 - enum:
23 - qcom,msm8916-iommu
24 - qcom,msm8953-iommu
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| /Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra194-cbb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sumit Gupta <sumitg@nvidia.com>
15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
31 - For other initiators, the ERD is disabled. So, the access issuing
34 include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
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| /Documentation/devicetree/bindings/mtd/ |
| D | nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
18 SPI-NAND devices are concerned by this description.
23 Contains the chip-select IDs.
25 nand-ecc-engine:
31 2/ The ECC engine is part of the NAND part (on-die), in this
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| /Documentation/arch/x86/ |
| D | amd-memory-encryption.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Secure Memory Encryption (SME) and Secure Encrypted Virtualization (SEV) are
17 of the guest VM are secured so that a decrypted version is available only
19 memory. Private memory is encrypted with the guest-specific key, while shared
39 is operating in 64-bit or 32-bit PAE mode, in all other modes the SEV hardware
52 memory encryption is enabled (this only affects
78 - Supported:
81 - Enabled:
84 - Active:
87 kernel is non-zero).
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